596c845072
Memory layout can now be specified via kconfig options. Two possibilities exist: default layout means the layout is stack / malloc heap / U-Boot. The user can also specify fixed addresses for each TEXT_BASE / stack / malloc heap.
47 lines
1.7 KiB
C
47 lines
1.7 KiB
C
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Clock settings
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#if defined(CONFIG_MACH_IPE337_V1)
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#define CONFIG_CLKIN_HZ 25000000
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#elif defined(CONFIG_MACH_IPE337_V2)
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#define CONFIG_CLKIN_HZ 40000000
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#else
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#error "Unknown IPE337 revision"
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#endif
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/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
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/* 1=CLKIN/2 */
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#define CONFIG_CLKIN_HALF 0
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/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
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/* 1=bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
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/* Values can range from 1-64 */
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#define CONFIG_VCO_MULT 10 /* POR default */
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/* CONFIG_CCLK_DIV controls what the core clock divider is */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1 /* POR default */
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/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5 /* POR default */
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/* Frequencies selected: 400MHz CCLK / 80MHz SCLK ^= 12.5ns cycle time*/
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#define AMGCTLVAL 0x1F
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/* no need for speed, currently, leave at defaults */
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#define AMBCTL0VAL 0xFFC2FFC2
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#define AMBCTL1VAL 0xFFC2FFC2
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#define CONFIG_MEM_MT48LC16M16A2TG_75 1
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#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
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#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
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#endif /* __CONFIG_H */
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