74cc7814eb
Also rewrite IOMUX to be a lot smaller, because of 2K limit. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
168 lines
4.4 KiB
ArmAsm
168 lines
4.4 KiB
ArmAsm
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx-pll.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.section ".text_bare_init","ax"
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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writel(IPU_CONF_DI_EN, IPU_CONF)
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writel(0x074B0BF5, IMX_CCM_BASE + CCM_CCMR)
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DELAY 0x40000
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writel(0x074B0BF5 | CCMR_MPE, IMX_CCM_BASE + CCM_CCMR)
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writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, IMX_CCM_BASE + CCM_CCMR)
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writel(PDR0_CSI_PODF(0xff1) | \
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PDR0_PER_PODF(7) | \
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PDR0_HSP_PODF(3) | \
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PDR0_NFC_PODF(5) | \
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PDR0_IPG_PODF(1) | \
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PDR0_MAX_PODF(3) | \
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PDR0_MCU_PODF(0), \
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IMX_CCM_BASE + CCM_PDR0)
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), IMX_CCM_BASE + CCM_MPCTL)
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), IMX_CCM_BASE + CCM_SPCTL)
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/* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched)
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* (behaviour copied by sha, source unknown)
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*/
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mov r1, #0;
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ldr r0, =0x43FAC26C
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str r1, [r0], #4
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str r1, [r0], #4
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str r1, [r0], #0x10
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ldr r2, =0x43FAC2DC
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clear_iomux:
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str r1, [r0], #4
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cmp r0, r2
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bls clear_iomux
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writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x80000000
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blo 1f
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cmp pc, #0x90000000
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bhs 1f
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mov pc, r10
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1:
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define ROWS0 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define ROWS0 ESDCTL0_ROW14
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#endif
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writel(0x00000004, ESDMISC)
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writel(0x006ac73a, ESDCFG0)
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writel(0x90100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0 + 0xf00)
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writel(0xa0100000 | ROWS0, ESDCTL0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0x12344321, IMX_SDRAM_CS0)
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writel(0xb0100000 | ROWS0, ESDCTL0)
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writeb(0xda, IMX_SDRAM_CS0 + 0x33)
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writeb(0xff, IMX_SDRAM_CS0 + 0x01000000)
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writel(0x80226080 | ROWS0, ESDCTL0)
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writel(0xDEADBEEF, IMX_SDRAM_CS0)
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writel(0x0000000c, ESDMISC)
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define ROWS1 ESDCTL0_ROW13
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define ROWS1 ESDCTL0_ROW14
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#endif
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writel(0x006ac73a, ESDCFG1)
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writel(0x90100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1 + 0xf00)
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writel(0xa0100000 | ROWS1, ESDCTL1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0x12344321, IMX_SDRAM_CS1)
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writel(0xb0100000 | ROWS1, ESDCTL1)
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writeb(0xda, IMX_SDRAM_CS1 + 0x33)
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writeb(0xff, IMX_SDRAM_CS1 + 0x01000000)
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writel(0x80226080 | ROWS1, ESDCTL1)
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writel(0xDEADBEEF, IMX_SDRAM_CS1)
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writel(0x0000000c, ESDMISC)
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#endif
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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blo ret
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cmp pc, r2
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bhs ret
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/* Move ourselves out of NFC SRAM */
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ldr r1, =TEXT_BASE
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copy_loop:
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ldmia r0!, {r3-r9} /* copy from source address [r0] */
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stmia r1!, {r3-r9} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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ldr pc, =1f /* Jump to SDRAM */
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1:
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bl nand_boot /* Load U-Boot from NAND Flash */
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ldr r1, =IMX_NFC_BASE - TEXT_BASE
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sub r10, r10, r1 /* adjust return address from NFC SRAM */
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ret:
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#endif /* CONFIG_NAND_IMX_BOOT */
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mov pc, r10
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