165 lines
3.7 KiB
C
165 lines
3.7 KiB
C
/*
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* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <sizes.h>
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#include <io.h>
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#include <asm/sections.h>
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#include <asm/mmu.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/imx6-mmdc.h>
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#include <mach/imx6-regs.h>
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#include <mach/generic.h>
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#include <debug_ll.h>
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static inline void early_uart_init(void)
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{
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writel(0x00000000, MX6_UART1_BASE_ADDR + 0x80);
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writel(0x00004027, MX6_UART1_BASE_ADDR + 0x84);
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writel(0x00000704, MX6_UART1_BASE_ADDR + 0x88);
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writel(0x00000a81, MX6_UART1_BASE_ADDR + 0x90);
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writel(0x0000002b, MX6_UART1_BASE_ADDR + 0x9c);
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writel(0x00013880, MX6_UART1_BASE_ADDR + 0xb0);
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writel(0x0000047f, MX6_UART1_BASE_ADDR + 0xa4);
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writel(0x0000c34f, MX6_UART1_BASE_ADDR + 0xa8);
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writel(0x00000001, MX6_UART1_BASE_ADDR + 0x80);
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putc_ll('>');
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}
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static inline void early_uart_init_6q(void)
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{
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writel(0x3, MX6_IOMUXC_BASE_ADDR + 0x280);
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writel(0x3, MX6_IOMUXC_BASE_ADDR + 0x284);
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writel(0x1, MX6_IOMUXC_BASE_ADDR + 0x920);
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writel(0x0001b0b1, MX6_IOMUXC_BASE_ADDR + 0x650);
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writel(0x0001b0b1, MX6_IOMUXC_BASE_ADDR + 0x654);
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early_uart_init();
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}
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static inline void early_uart_init_6s(void)
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{
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writel(0x3, MX6_IOMUXC_BASE_ADDR + 0x4c);
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writel(0x3, MX6_IOMUXC_BASE_ADDR + 0x50);
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writel(0x1, MX6_IOMUXC_BASE_ADDR + 0x8fc);
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writel(0x0001b0b1, MX6_IOMUXC_BASE_ADDR + 0x360);
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writel(0x0001b0b1, MX6_IOMUXC_BASE_ADDR + 0x364);
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early_uart_init();
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}
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static inline unsigned int memsize_512M_1G(void)
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{
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volatile u32 *a = (u32 *)0x10000000;
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volatile u32 *b = (u32 *)0x30000000;
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u32 size;
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*a = 0x55555555;
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*b = 0xaaaaaaaa;
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if (*a == 0xaaaaaaaa)
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size = SZ_512M;
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else
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size = SZ_1G;
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*a = size;
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return size;
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}
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static inline unsigned int memsize_1G_2G(void)
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{
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volatile u32 *a = (u32 *)0x10000000;
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volatile u32 *b = (u32 *)0x50000000;
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u32 size;
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*a = 0x55555555;
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*b = 0xaaaaaaaa;
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if (*a == 0xaaaaaaaa)
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size = SZ_1G;
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else
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size = SZ_2G;
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*a = size;
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return size;
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}
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extern char __dtb_imx6q_dfi_fs700_m60_6q_start[];
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ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_nanya, r0, r1, r2)
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{
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void *fdt;
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int i;
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imx6_cpu_lowlevel_init();
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arm_setup_stack(0x00940000 - 8);
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for (i = 0x68; i <= 0x80; i += 4)
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writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
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early_uart_init_6q();
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fdt = __dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
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barebox_arm_entry(0x10000000, memsize_1G_2G(), fdt);
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}
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ENTRY_FUNCTION(start_imx6q_dfi_fs700_m60_6q_micron, r0, r1, r2)
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{
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void *fdt;
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int i;
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imx6_cpu_lowlevel_init();
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arm_setup_stack(0x00940000 - 8);
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for (i = 0x68; i <= 0x80; i += 4)
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writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
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early_uart_init_6q();
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fdt = __dtb_imx6q_dfi_fs700_m60_6q_start - get_runtime_offset();
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*(uint32_t *)0x10000000 = SZ_1G;
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barebox_arm_entry(0x10000000, SZ_1G, fdt);
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}
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extern char __dtb_imx6dl_dfi_fs700_m60_6s_start[];
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ENTRY_FUNCTION(start_imx6dl_dfi_fs700_m60_6s, r0, r1, r2)
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{
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void *fdt;
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int i;
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imx6_cpu_lowlevel_init();
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arm_setup_stack(0x00920000 - 8);
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for (i = 0x68; i <= 0x80; i += 4)
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writel(0xffffffff, MX6_CCM_BASE_ADDR + i);
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early_uart_init_6s();
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fdt = __dtb_imx6dl_dfi_fs700_m60_6s_start - get_runtime_offset();
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barebox_arm_entry(0x10000000, memsize_512M_1G(), fdt);
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}
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