182 lines
4.5 KiB
C
182 lines
4.5 KiB
C
/*
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* Copyright 2014 GE Intelligent Platforms, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <ns16550.h>
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#include <net.h>
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#include <types.h>
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#include <i2c/i2c.h>
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#include <partition.h>
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#include <memory.h>
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#include <asm/cache.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#include <mach/mpc85xx.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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#include <mach/gianfar.h>
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#include <mach/clock.h>
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#include <mach/early_udelay.h>
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/* Define attributes for eTSEC1 and eTSEC2 */
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static struct gfar_info_struct gfar_info[] = {
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{
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.phyaddr = 1,
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.tbiana = 0,
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.tbicr = 0,
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.mdiobus_tbi = 0,
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},
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{
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.phyaddr = 2,
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.tbiana = 0,
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.tbicr = 0,
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.mdiobus_tbi = 0,
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},
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};
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struct i2c_platform_data i2cplat[] = {
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{ .bitrate = 400000, },
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{ .bitrate = 400000, },
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};
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void p1022ds_lbc_early_init(void)
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{
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void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR);
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void __iomem *lbc = LBC_BASE_ADDR;
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/* Set the local bus monitor timeout value to the maximum */
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clrsetbits_be32(lbc + FSL_LBC_LBCR_OFFSET, 0xff0f, 0xf);
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/* Set the pin muxing to enable ETSEC2. */
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clrbits_be32(gur + MPC85xx_GUTS_PMUXCR2_OFFSET, 0x001f8000);
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(gur + MPC85xx_GUTS_PMUXCR_OFFSET, 0x1000);
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/* Map the boot flash and FPGA */
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fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V);
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fsl_set_lbc_or(0, 0xf8000ff7);
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fsl_set_lbc_br(2, BR_PHYS_ADDR(CFG_PIXIS_BASE_PHYS) | BR_PS_8 | BR_V);
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fsl_set_lbc_or(2, 0xffff8ff7);
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}
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static void board_eth_init(void)
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{
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struct i2c_adapter *adapter;
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struct i2c_client client;
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char mac[6];
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int ret, ix;
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adapter = i2c_get_adapter(1);
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client.addr = 0x57;
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client.adapter = adapter;
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for (ix = 0; ix < 2; ix++) {
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int mac_offset;
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mac_offset = 0x42 + (sizeof(mac) * ix);
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ret = i2c_read_reg(&client, mac_offset, mac, sizeof(mac));
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if (ret != sizeof(mac))
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pr_err("Fail to retrieve MAC address\n");
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else
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eth_register_ethaddr(ix, mac);
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}
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fsl_eth_init(1, &gfar_info[0]);
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fsl_eth_init(2, &gfar_info[1]);
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}
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static int p1022ds_devices_init(void)
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{
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 128 << 20, 0);
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devfs_add_partition("nor0", 0x7f80000, 0x80000, DEVFS_PARTITION_FIXED,
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"self0");
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devfs_add_partition("nor0", 0x7f00000, 0x10000, DEVFS_PARTITION_FIXED,
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"env0");
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add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100,
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IORESOURCE_MEM, &i2cplat[0]);
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add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100,
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IORESOURCE_MEM, &i2cplat[1]);
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board_eth_init();
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return 0;
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}
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device_initcall(p1022ds_devices_init);
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static struct NS16550_plat serial_plat = {
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.clock = 0,
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.shift = 0,
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};
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static int p1022ds_console_init(void)
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{
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barebox_set_model("Freescale P1022DS");
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barebox_set_hostname("p1022ds");
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(DEVICE_ID_DYNAMIC, CFG_IMMR + 0x4500, 16,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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}
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console_initcall(p1022ds_console_init);
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static int p1022ds_mem_init(void)
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{
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barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize());
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return 0;
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}
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mem_initcall(p1022ds_mem_init);
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static int p1022ds_board_init_r(void)
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{
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void __iomem *fpga = IOMEM(CFG_PIXIS_BASE);
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const uint32_t flashbase = CFG_BOOT_BLOCK;
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const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
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/* Enable SPI */
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out_8(fpga + 8, (in_8(fpga + 8) & ~(0xc0)) | (0x80));
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/* Map the NAND flash */
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fsl_set_lbc_br(1, BR_PHYS_ADDR(0xff800000) | BR_PS_8 |
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(2 << BR_DECC_SHIFT) | BR_MS_FCM | BR_V);
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fsl_set_lbc_or(1, 0xffff8796);
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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e500_disable_tlb(flash_esel);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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e500_set_tlb(1, flashbase, CFG_BOOT_BLOCK_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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fsl_l2_cache_init();
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return 0;
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}
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core_initcall(p1022ds_board_init_r);
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