267 lines
7.0 KiB
C
267 lines
7.0 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <ns16550.h>
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#include <types.h>
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#include <i2c/i2c.h>
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#include <partition.h>
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#include <memory.h>
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#include <asm/cache.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#include <mach/mpc85xx.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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#include <mach/gianfar.h>
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#include <mach/clock.h>
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#include <mach/early_udelay.h>
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#define VSC7385_RST_SET 0x00080000
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#define SLIC_RST_SET 0x00040000
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#define SGMII_PHY_RST_SET 0x00020000
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#define PCIE_RST_SET 0x00010000
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#define RGMII_PHY_RST_SET 0x02000000
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#define USB_RST_CLR 0x04000000
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#define GPIO_DIR 0x060f0000
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#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
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SGMII_PHY_RST_SET | PCIE_RST_SET | \
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RGMII_PHY_RST_SET)
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#define SYSCLK_MASK 0x00200000
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#define BOARDREV_MASK 0x10100000
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#define BOARDREV_B 0x10100000
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#define BOARDREV_C 0x00100000
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#define BOARDREV_D 0x00000000
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#define SYSCLK_66 66666666
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#define SYSCLK_50 50000000
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#define SYSCLK_100 100000000
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/* Define attributes for eTSEC2 and eTSEC3 */
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static struct gfar_info_struct gfar_info[] = {
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{
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.phyaddr = 0,
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.tbiana = 0x1a0,
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.tbicr = 0x9140,
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.mdiobus_tbi = 1,
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},
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{
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.phyaddr = 1,
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.tbiana = 0,
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.tbicr = 0,
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.mdiobus_tbi = 2,
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},
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};
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/* I2C busses. */
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struct i2c_platform_data i2cplat = {
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.bitrate = 400000,
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};
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static int devices_init(void)
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{
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, CFG_FLASH_BASE, 16 << 20, 0);
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devfs_add_partition("nor0", 0xf60000, 0x8000, DEVFS_PARTITION_FIXED,
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"env0");
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devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
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"self0");
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add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR,
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0x100, IORESOURCE_MEM, &i2cplat);
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add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR,
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0x100, IORESOURCE_MEM, &i2cplat);
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fsl_eth_init(2, &gfar_info[0]);
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fsl_eth_init(3, &gfar_info[1]);
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return 0;
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}
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device_initcall(devices_init);
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static struct NS16550_plat serial_plat = {
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.clock = 0,
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.shift = 0,
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};
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static int p2020_console_init(void)
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{
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barebox_set_model("Freescale P2020RDB");
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barebox_set_hostname("p2020rdb");
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(DEVICE_ID_DYNAMIC, 0xffe04500, 16,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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&serial_plat);
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return 0;
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}
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console_initcall(p2020_console_init);
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static int mem_init(void)
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{
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barebox_add_memory_bank("ram0", 0x0, 1024 << 20);
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return 0;
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}
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mem_initcall(mem_init);
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/*
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* fixed_sdram: fixed sdram settings.
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*/
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phys_size_t fixed_sdram(void)
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{
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void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR);
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int sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN |
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SDRAM_CFG_SDRAM_TYPE_DDR2);
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phys_size_t dram_size;
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/* If already enabled (running from RAM), get out */
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if (in_be32(regs + DDR_OFF(SDRAM_CFG)) & SDRAM_CFG_MEM_EN)
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return fsl_get_effective_memsize();
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out_be32(regs + DDR_OFF(CS0_BNDS), CFG_SYS_DDR_CS0_BNDS);
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out_be32(regs + DDR_OFF(CS0_CONFIG), CFG_SYS_DDR_CS0_CONFIG);
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out_be32(regs + DDR_OFF(TIMING_CFG_3), CFG_SYS_DDR_TIMING_3);
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out_be32(regs + DDR_OFF(TIMING_CFG_0), CFG_SYS_DDR_TIMING_0);
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out_be32(regs + DDR_OFF(TIMING_CFG_1), CFG_SYS_DDR_TIMING_1);
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out_be32(regs + DDR_OFF(TIMING_CFG_2), CFG_SYS_DDR_TIMING_2);
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out_be32(regs + DDR_OFF(SDRAM_CFG_2), CFG_SYS_DDR_CONTROL2);
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out_be32(regs + DDR_OFF(SDRAM_MODE), CFG_SYS_DDR_MODE_1);
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out_be32(regs + DDR_OFF(SDRAM_MODE_2), CFG_SYS_DDR_MODE_2);
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out_be32(regs + DDR_OFF(SDRAM_MD_CNTL), CFG_SYS_MD_CNTL);
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/* Basic refresh rate (7.8us),high temp is 3.9us */
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out_be32(regs + DDR_OFF(SDRAM_INTERVAL),
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CFG_SYS_DDR_INTERVAL);
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out_be32(regs + DDR_OFF(SDRAM_DATA_INIT),
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CFG_SYS_DDR_DATA_INIT);
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out_be32(regs + DDR_OFF(SDRAM_CLK_CNTL),
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CFG_SYS_DDR_CLK_CTRL);
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out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR), 0);
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out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR_EXT), 0);
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/*
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* Wait 200us for the DDR clock to stabilize.
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*/
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early_udelay(200);
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asm volatile ("sync;isync");
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out_be32(regs + DDR_OFF(SDRAM_CFG), sdram_cfg);
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dram_size = fsl_get_effective_memsize();
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if (fsl_set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR) < 0)
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return 0;
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return dram_size;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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u32 val_gpdat, sysclk_gpio, board_rev_gpio;
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void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR;
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val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT);
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sysclk_gpio = val_gpdat & SYSCLK_MASK;
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board_rev_gpio = val_gpdat & BOARDREV_MASK;
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if (board_rev_gpio == BOARDREV_C) {
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if (sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_100;
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} else if (board_rev_gpio == BOARDREV_B) {
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if (sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_50;
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} else if (board_rev_gpio == BOARDREV_D) {
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if (sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_100;
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}
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return 0;
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}
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static void checkboard(void)
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{
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u32 val_gpdat, board_rev_gpio;
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void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR;
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val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT);
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board_rev_gpio = val_gpdat & BOARDREV_MASK;
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if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) &&
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(board_rev_gpio != BOARDREV_D))
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panic("Unexpected Board REV %x detected!!\n", board_rev_gpio);
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setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR);
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/*
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* Bringing the following peripherals out of reset via GPIOs
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* 0 = reset and 1 = out of reset
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* GPIO12 - Reset to Ethernet Switch
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* GPIO13 - Reset to SLIC/SLAC devices
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* GPIO14 - Reset to SGMII_PHY_N
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* GPIO15 - Reset to PCIe slots
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* GPIO6 - Reset to RGMII PHY
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* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
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*/
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clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR,
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BOARD_PERI_RST_SET);
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}
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static int board_init_r(void)
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{
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const unsigned int flashbase = CFG_FLASH_BASE;
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const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
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checkboard();
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/* Map the whole boot flash */
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fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V);
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fsl_set_lbc_or(0, 0xff000ff7);
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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e500_disable_tlb(flash_esel);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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e500_set_tlb(1, flashbase, CFG_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_16M, 1);
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fsl_l2_cache_init();
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return 0;
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}
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core_initcall(board_init_r);
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