214 lines
5.3 KiB
C
214 lines
5.3 KiB
C
/*
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* Copyright 2013 GE Intelligent Platforms, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* GEIP DA923RC/GBX460 board support.
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*/
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#include <common.h>
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#include <console.h>
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#include <init.h>
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#include <memory.h>
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#include <driver.h>
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#include <asm/io.h>
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#include <net.h>
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#include <ns16550.h>
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#include <partition.h>
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#include <environment.h>
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#include <i2c/i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/cache.h>
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#include <mach/mmu.h>
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#include <mach/mpc85xx.h>
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#include <mach/immap_85xx.h>
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#include <mach/gianfar.h>
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#include <mach/gpio.h>
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#include <mach/clock.h>
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#include <mach/fsl_i2c.h>
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#include "product_data.h"
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static struct gfar_info_struct gfar_info[] = {
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{
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.phyaddr = 7,
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.tbiana = 0,
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.tbicr = 0,
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.mdiobus_tbi = 0,
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},
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};
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struct i2c_platform_data i2cplat[] = {
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{
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.bitrate = 400000,
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},
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{
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.bitrate = 400000,
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},
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};
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static struct board_info binfo;
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static int board_eth_init(void)
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{
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void __iomem *gur = IOMEM(MPC85xx_GUTS_ADDR);
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struct ge_product_data product;
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int st;
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/* Toggle eth0 reset pin */
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gpio_set_value(4, 0);
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udelay(5);
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gpio_set_value(4, 1);
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/* Disable eTSEC3 */
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out_be32(gur + MPC85xx_DEVDISR_OFFSET,
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in_be32(gur + MPC85xx_DEVDISR_OFFSET) &
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~MPC85xx_DEVDISR_TSEC3);
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st = ge_get_product_data(&product);
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if (((product.v2.mac.count > 0) && (product.v2.mac.count <= MAX_MAC))
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&& (st == 0))
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eth_register_ethaddr(0, (const char *)&product.v2.mac.mac[0]);
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fsl_eth_init(1, &gfar_info[0]);
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return 0;
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}
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static int da923rc_devices_init(void)
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{
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add_cfi_flash_device(0, 0xfe000000, 32 << 20, 0);
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devfs_add_partition("nor0", 0x0, 0x8000, DEVFS_PARTITION_FIXED, "env0");
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devfs_add_partition("nor0", 0x1f80000, 8 << 16, DEVFS_PARTITION_FIXED,
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"self0");
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add_generic_device("i2c-fsl", 0, NULL, I2C1_BASE_ADDR, 0x100,
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IORESOURCE_MEM, &i2cplat[0]);
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add_generic_device("i2c-fsl", 1, NULL, I2C2_BASE_ADDR, 0x100,
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IORESOURCE_MEM, &i2cplat[1]);
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board_eth_init();
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return 0;
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}
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device_initcall(da923rc_devices_init);
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static struct NS16550_plat serial_plat = {
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.clock = 0,
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.shift = 0,
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};
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static int da923rc_console_init(void)
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{
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if (binfo.bid == BOARD_TYPE_DA923)
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barebox_set_model("DA923RC");
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else if (binfo.bid == BOARD_TYPE_GBX460)
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barebox_set_model("GBX460");
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else
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barebox_set_model("unknown");
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serial_plat.clock = fsl_get_bus_freq(0);
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add_ns16550_device(1, CFG_CCSRBAR + 0x4600, 16,
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IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
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&serial_plat);
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return 0;
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}
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console_initcall(da923rc_console_init);
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static int da923rc_mem_init(void)
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{
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barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize());
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return 0;
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}
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mem_initcall(da923rc_mem_init);
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static int da923rc_board_init_r(void)
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{
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void __iomem *lbc = LBC_BASE_ADDR;
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void __iomem *ecm = IOMEM(MPC85xx_ECM_ADDR);
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void __iomem *pci = IOMEM(PCI1_BASE_ADDR);
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const unsigned int flashbase = (BOOT_BLOCK + 0x2000000);
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uint8_t flash_esel;
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da923rc_boardinfo_get(&binfo);
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flush_dcache();
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invalidate_icache();
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/* Clear LBC error interrupts */
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out_be32(lbc + FSL_LBC_LTESR_OFFSET, 0xffffffff);
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/* Enable LBC error interrupts */
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out_be32(lbc + FSL_LBC_LTEIR_OFFSET, 0xffffffff);
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/* Clear ecm errors */
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out_be32(ecm + MPC85xx_ECM_EEDR_OFFSET, 0xffffffff);
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/* Enable ecm errors */
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out_be32(ecm + MPC85xx_ECM_EEER_OFFSET, 0xffffffff);
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/* Re-map boot flash */
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fsl_set_lbc_br(0, BR_PHYS_ADDR(0xfe000000) | BR_PS_16 | BR_V);
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fsl_set_lbc_or(0, 0xfe006e21);
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/* Invalidate TLB entry for boot block */
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flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
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e500_disable_tlb(flash_esel);
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flash_esel = e500_find_tlb_idx((void *)(flashbase + 0x1000000), 1);
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e500_disable_tlb(flash_esel);
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/* Boot block back to cache inhibited. */
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e500_set_tlb(1, BOOT_BLOCK + (2 * 0x1000000),
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BOOT_BLOCK + (2 * 0x1000000),
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M,
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0, 2, BOOKE_PAGESZ_16M, 1);
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e500_set_tlb(1, BOOT_BLOCK + (3 * 0x1000000),
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BOOT_BLOCK + (3 * 0x1000000),
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G | MAS2_M,
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0, 3, BOOKE_PAGESZ_16M, 1);
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fsl_l2_cache_init();
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fsl_enable_gpiout();
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/* Enable NOR low voltage programming (gpio 2) and write (gpio 3). */
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gpio_set_value(2, 1);
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gpio_set_value(3, 1);
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/* Enable write to NAND flash */
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if (binfo.bid == BOARD_TYPE_GBX460) {
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/* Map CPLD */
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fsl_set_lbc_br(3, BR_PHYS_ADDR(0xfc010000) | BR_PS_16 | BR_V);
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fsl_set_lbc_or(3, 0xffffe001);
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/* Enable all reset */
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out_be16(IOMEM(0xfc010044), 0xffff);
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gpio_set_value(6, 1);
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}
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/* Board reset and PHY reset. Disable CS3. */
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if (binfo.bid == BOARD_TYPE_DA923) {
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gpio_set_value(0, 0);
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gpio_set_value(1, 1);
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/* De-assert Board reset */
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udelay(1000);
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gpio_set_value(0, 1);
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}
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/* Enable PCI error reporting */
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out_be32(pci + 0xe00, 0x80000040);
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out_be32(pci + 0xe08, 0x6bf);
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out_be32(pci + 0xe0c, 0xbb1fa001);
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/* 32-bytes cacheline size */
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out_be32(pci, 0x8000000c);
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out_le32(pci + 4, 0x00008008);
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return 0;
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}
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postcore_initcall(da923rc_board_init_r);
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