95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/*
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* Copyright 2013 GE Intelligent Platforms, Inc
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* (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
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* (C) Copyright 2006
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* Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This code only cares about setting up the UPM state machine for Linux
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* to use the NAND.
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/fsl_lbc.h>
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#include <mach/immap_85xx.h>
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/* NAND UPM tables for a 25Mhz bus frequency. */
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static const u32 upm_patt_25[] = {
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/* Single read data */
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0xcff02c30, 0x0ff02c30, 0x0ff02c34, 0x0ff32c30,
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0xfff32c31, 0xfff32c30, 0xfffffc30, 0xfffffc30,
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/* UPM Read Burst RAM array entry -> NAND Write CMD */
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0xcfaf2c30, 0x0faf2c30, 0x0faf2c30, 0x0fff2c34,
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0xfffffc31, 0xfffffc30, 0xfffffc30, 0xfffffc30,
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/* UPM Read Burst RAM array entry -> NAND Write ADDR */
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0xcfa3ec30, 0x0fa3ec30, 0x0fa3ec30, 0x0ff3ec34,
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0xfff3ec31, 0xfffffc30, 0xfffffc30, 0xfffffc30,
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/* UPM Write Single RAM array entry -> NAND Write Data */
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0x0ff32c30, 0x0fa32c30, 0x0fa32c34, 0x0ff32c30,
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0xfff32c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30,
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/* Default */
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0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30,
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0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30,
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0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30,
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0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31,
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0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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};
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static void upm_write(uint8_t addr, uint32_t val)
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{
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void __iomem *lbc = LBC_BASE_ADDR;
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out_be32(lbc + FSL_LBC_MDR_OFFSET, val);
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clrsetbits_be32(lbc + FSL_LBC_MAMR_OFFSET, MxMR_MAD_MSK,
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MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
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/* dummy access to perform write */
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out_8(IOMEM(0xfc000000), 0);
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clrbits_be32(lbc + FSL_LBC_MAMR_OFFSET, MxMR_OP_WARR);
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}
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static int board_nand_init(void)
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{
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void __iomem *mxmr = IOMEM(LBC_BASE_ADDR + FSL_LBC_MAMR_OFFSET);
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int j;
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/* Base register CS2:
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* - 0xfc000000
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* - 8-bit data width
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* - UPMA
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*/
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fsl_set_lbc_br(2, BR_PHYS_ADDR(0xfc000000) | BR_PS_8 | BR_MS_UPMA |
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BR_V);
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/*
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* Otions register:
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* - 32KB window.
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* - Buffer control disabled.
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* - External address latch delay.
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*/
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fsl_set_lbc_or(2, 0xffffe001);
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for (j = 0; j < 64; j++)
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upm_write(j, upm_patt_25[j]);
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out_be32(mxmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
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return 0;
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}
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device_initcall(board_nand_init);
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