4586f9626b
From Kernel commit 418df63a ARM: 7670/1: fix the memset fix
| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value. However the memset itself became broken
| by that patch for misaligned pointers.
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| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
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| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
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| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
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| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
125 lines
2.3 KiB
ArmAsm
125 lines
2.3 KiB
ArmAsm
/*
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* linux/arch/arm/lib/memset.S
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*
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* Copyright (C) 1995-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ASM optimised string functions
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.align 5
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ENTRY(memset)
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ands r3, r0, #3 @ 1 unaligned?
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mov ip, r0 @ preserve r0 as return value
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bne 6f @ 1
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/*
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* we know that the pointer in ip is aligned to a word boundary.
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*/
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1: orr r1, r1, r1, lsl #8
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orr r1, r1, r1, lsl #16
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mov r3, r1
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cmp r2, #16
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blt 4f
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#if ! CALGN(1)+0
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/*
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* We need an 2 extra registers for this loop - use r8 and the LR
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*/
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stmfd sp!, {r8, lr}
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mov r8, r1
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mov lr, r1
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2: subs r2, r2, #64
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stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
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stmgeia ip!, {r1, r3, r8, lr}
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stmgeia ip!, {r1, r3, r8, lr}
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stmgeia ip!, {r1, r3, r8, lr}
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bgt 2b
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ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
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/*
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* No need to correct the count; we're only testing bits from now on
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*/
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tst r2, #32
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stmneia ip!, {r1, r3, r8, lr}
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stmneia ip!, {r1, r3, r8, lr}
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tst r2, #16
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stmneia ip!, {r1, r3, r8, lr}
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ldmfd sp!, {r8, lr}
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#else
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/*
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* This version aligns the destination pointer in order to write
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* whole cache lines at once.
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*/
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stmfd sp!, {r4-r8, lr}
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mov r4, r1
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mov r5, r1
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mov r6, r1
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mov r7, r1
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mov r8, r1
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mov lr, r1
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cmp r2, #96
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tstgt ip, #31
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ble 3f
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and r8, ip, #31
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rsb r8, r8, #32
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sub r2, r2, r8
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movs r8, r8, lsl #(32 - 4)
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stmcsia ip!, {r4, r5, r6, r7}
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stmmiia ip!, {r4, r5}
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tst r8, #(1 << 30)
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mov r8, r1
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strne r1, [ip], #4
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3: subs r2, r2, #64
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stmgeia ip!, {r1, r3-r8, lr}
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stmgeia ip!, {r1, r3-r8, lr}
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bgt 3b
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ldmeqfd sp!, {r4-r8, pc}
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tst r2, #32
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stmneia ip!, {r1, r3-r8, lr}
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tst r2, #16
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stmneia ip!, {r4-r7}
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ldmfd sp!, {r4-r8, lr}
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#endif
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4: tst r2, #8
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stmneia ip!, {r1, r3}
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tst r2, #4
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strne r1, [ip], #4
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/*
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* When we get here, we've got less than 4 bytes to zero. We
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* may have an unaligned pointer as well.
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*/
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5: tst r2, #2
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strneb r1, [ip], #1
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strneb r1, [ip], #1
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tst r2, #1
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strneb r1, [ip], #1
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mov pc, lr
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6: subs r2, r2, #4 @ 1 do we have enough
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blt 5b @ 1 bytes to align with?
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cmp r3, #2 @ 1
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strltb r1, [ip], #1 @ 1
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strleb r1, [ip], #1 @ 1
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strb r1, [ip], #1 @ 1
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add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
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b 1b
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ENDPROC(memset)
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