2cf467ec07
The esdctl devices are currently not in the devicetrees. this means they are not registered when booting from the devicetree. Move the device registration from soc_devices_init to soc_init which is called even with devicetree support so that we get esdctl devices. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <sizes.h>
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#include <init.h>
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#include <io.h>
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#include <mach/weim.h>
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#include <mach/imx35-regs.h>
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#include <mach/iim.h>
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#include <mach/revision.h>
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#include <mach/generic.h>
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void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower,
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unsigned additional)
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{
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writel(upper, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
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writel(lower, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
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writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8);
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}
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static void imx35_silicon_revision(void)
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{
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uint32_t reg;
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reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
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/* 0×00 = TO 1.0, First silicon */
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reg += IMX_CHIP_REV_1_0;
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imx_set_silicon_revision("i.MX35", reg & 0xFF);
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}
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/*
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* There are some i.MX35 CPUs in the wild, comming with bogus L2 cache settings.
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* These misconfigured CPUs will run amok immediately when the L2 cache gets
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* enabled. Workaraound is to setup the correct register setting prior enabling
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* the L2 cache. This should not hurt already working CPUs, as they are using the
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* same value
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*/
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#define L2_MEM_VAL 0x10
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int imx35_init(void)
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{
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writel(0x515, MX35_CLKCTL_BASE_ADDR + L2_MEM_VAL);
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imx35_silicon_revision();
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imx35_boot_save_loc((void *)MX35_CCM_BASE_ADDR);
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add_generic_device("imx35-esdctl", 0, NULL, MX35_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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return 0;
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}
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int imx35_devices_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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add_generic_device("imx-iomuxv3", 0, NULL, MX35_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx21-wdt", 0, NULL, MX35_WDOG_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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return 0;
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}
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