59a22cb392
What we had as usb phy1 base address is really usb phy2. Fix the names and add the missing base address definition for usb phy1. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
/*
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* Copyright (C) 2012 Steffen Trumtrar, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/imx6-regs.h>
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#define SET 0x4
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#define CLR 0x8
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#define USBPHY_CTRL 0x30
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#define USB_OTG_CTRL 0x800
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#define USB_UH1_CTRL 0x804
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#define USB_UH2_CTRL 0x808
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#define USB_UH3_CTRL 0x80c
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#define USB_UH1_USBCMD 0x340
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#define USB_CMD_RUNSTOP (1 << 0)
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#define USB_CMD_RESET (1 << 1)
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#define USB_OVER_CUR_DIS (1 << 7)
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#define USBPHY_CTRL_SFTRST (1 << 31)
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#define USBPHY_CTRL_CLKGATE (1 << 30)
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#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15)
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#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14)
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#define USBPHY1_PLL_480_CTRL_EN (1 << 13)
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#define USBPHY1_PLL_480_CTRL_POWER (1 << 12)
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#define USBPHY1_PLL_480_CTRL_EN_USB_CLK (1 << 6)
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#define USBPHY1_PLL_480_CTRL_BYPASS (1 << 16)
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int imx6_usb_phy2_disable_oc(void)
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{
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int val;
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/* disable over current detection */
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val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_CTRL);
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val |= USB_OVER_CUR_DIS;
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writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_CTRL);
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val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH2_CTRL);
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val |= USB_OVER_CUR_DIS;
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writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH2_CTRL);
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val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH3_CTRL);
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val |= USB_OVER_CUR_DIS;
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writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH3_CTRL);
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return 0;
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}
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int imx6_usb_phy2_enable(void)
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{
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int val;
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/* disable external charger detector or DP will be poor */
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writel(0x00180000, MX6_ANATOP_BASE_ADDR + 0x1b0);
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writel(0x00180000, MX6_ANATOP_BASE_ADDR + 0x210);
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/* enable usb pll */
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writel(USBPHY1_PLL_480_CTRL_EN |
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USBPHY1_PLL_480_CTRL_POWER |
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USBPHY1_PLL_480_CTRL_EN_USB_CLK, MX6_ANATOP_BASE_ADDR + 0x24);
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/* turn OFF clk bypass */
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/* at least on imx6 v1.0 this essential for usb to work */
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/* FIXME: test on v1.1. Datasheet declares bit as reserved */
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writel(USBPHY1_PLL_480_CTRL_BYPASS, MX6_ANATOP_BASE_ADDR + 0x28);
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/* stop then reset */
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val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD);
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val &= ~USB_CMD_RUNSTOP;
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writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD);
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while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RUNSTOP);
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val = readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD);
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val |= USB_CMD_RESET;
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writel(val, MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD);
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while (readl(MX6_USBOH3_USB_BASE_ADDR + USB_UH1_USBCMD) & USB_CMD_RESET);
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/* reset usbphy */
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writel(USBPHY_CTRL_SFTRST, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET);
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udelay(10);
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/* clr reset and clkgate */
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writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + CLR);
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/* clr all pwd bits => power up phy */
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writel(0xffffffff, MX6_USBPHY2_BASE_ADDR + CLR);
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/* set utmilvl2/3 */
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val = readl(MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL);
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val |= USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2;
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writel(val, MX6_USBPHY2_BASE_ADDR + USBPHY_CTRL + SET);
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return 0;
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}
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