250 lines
7.0 KiB
ArmAsm
250 lines
7.0 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM CPU-cores
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*
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* Copyright (c) 2001 Marius Gr<EFBFBD>ger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Z<EFBFBD>pke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/**
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* @file
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* @brief The very basic beginning of each CPU after reset
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*
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* @note
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* This reset code can be used at least for:
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* - ARM920T
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* - i.MX1
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* - i.MX27
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* - i.MX31
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*
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* FIXME: Stop doxygen from parsing the text below
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*/
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.section ".text_entry","ax"
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#include <config.h>
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#include <asm-generic/memory_layout.h>
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/*************************************************************************
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* Jump vector table as in table 3.1 in [1]
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*************************************************************************/
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.globl _start
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_start:
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b reset
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction: .word undefined_instruction
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_software_interrupt: .word software_interrupt
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_prefetch_abort: .word prefetch_abort
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_data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _barebox_start
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_barebox_start:
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.word _start
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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_TEXT_BASE:
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.word _stext
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_MALLOC_BASE:
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.word MALLOC_BASE
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_STACK_START:
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.word STACK_BASE + STACK_SIZE - 4
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory */
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IRQ_STACK_START:
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.word STACK_BASE + CONFIG_STACKSIZE_IRQ - 4
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/* IRQ stack memory */
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FIQ_STACK_START:
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.word STACK_BASE + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ - 4
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#endif
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/*************************************************************************
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* the actual reset code
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*************************************************************************/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
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bl arch_init_lowlevel
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#endif
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#ifdef CONFIG_CPU_V7
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/*
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* Invalidate v7 I/D caches
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*/
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mov r0, #0 /* set up for MCR */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
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/* Invalidate all Dcaches */
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#ifndef CONFIG_CPU_V7_DCACHE_SKIP
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/* If Arch specific ROM code SMI handling does not exist */
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mrc p15, 1, r0, c0, c0, 1 /* read clidr */
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ands r3, r0, #0x7000000 /* extract loc from clidr */
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mov r3, r3, lsr #23 /* left align loc bit field */
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beq finished_inval /* if loc is 0, then no need to clean */
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mov r10, #0 /* start clean at cache level 0 */
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inval_loop1:
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add r2, r10, r10, lsr #1 /* work out 3x current cache level */
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mov r1, r0, lsr r2 /* extract cache type bits from clidr */
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and r1, r1, # 7 /* mask of the bits for current cache only */
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cmp r1, #2 /* see what cache we have at this level */
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blt skip_inval /* skip if no cache, or just i-cache */
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mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
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isb /* isb to sych the new cssr&csidr */
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mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */
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and r2, r1, #7 /* extract the length of the cache lines */
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add r2, r2, #4 /* add 4 (line length offset) */
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/
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clz r5, r4 /* find bit position of way size increment */
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 /* extract max number of the index size */
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inval_loop2:
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mov r9, r4 /* create working copy of max way size */
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inval_loop3:
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orr r11, r10, r9, lsl r5 /* factor way and cache number into r11*/
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orr r11, r11, r7, lsl r2 /* factor index number into r11 */
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mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
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subs r9, r9, #1 /* decrement the way */
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bge inval_loop3
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subs r7, r7, #1 /* decrement the index */
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bge inval_loop2
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skip_inval:
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add r10, r10, #2 /* increment cache number */
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cmp r3, r10
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bgt inval_loop1
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finished_inval:
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mov r10, #0 /* swith back to cache level 0 */
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mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
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isb
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#endif /* CONFIG_CPU_V7_DCACHE_SKIP */
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#else
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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#endif
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT
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bl board_init_lowlevel
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#endif
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relocate: /* relocate barebox to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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ldr r2, _barebox_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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/* Set up the stack */
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stack_setup:
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ldr r0, _STACK_START
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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clbss_l:
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str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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ble clbss_l
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ldr pc, _start_armboot
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_start_armboot:
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.word start_barebox
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