144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/*
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* (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MX25_REGS_H
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#define __ASM_ARCH_MX35_REGS_H
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/*
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* sanity check
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*/
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#ifndef _IMX_REGS_H
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# error "Please do not include directly. Use imx-regs.h instead."
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#endif
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#define IMX_L2CC_BASE 0x30000000
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#define IMX_UART1_BASE 0x43F90000
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#define IMX_UART2_BASE 0x43F94000
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#define IMX_TIM1_BASE 0x53F90000
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#define IMX_IOMUXC_BASE 0x43FAC000
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#define IMX_WDT_BASE 0x53FDC000
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#define IMX_MAX_BASE 0x43F04000
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#define IMX_ESD_BASE 0xb8001000
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#define IMX_AIPS1_BASE 0x43F00000
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#define IMX_AIPS2_BASE 0x53F00000
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#define IMX_CCM_BASE 0x53F80000
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#define IMX_IIM_BASE 0x53FF0000
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#define IMX_OTG_BASE 0x53FF4000
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#define IMX_M3IF_BASE 0xB8003000
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#define IMX_NFC_BASE 0xBB000000
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#define IMX_FEC_BASE 0x50038000
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/*
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* Clock Controller Module (CCM)
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*/
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#define CCM_MPCTL 0x00
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#define CCM_UPCTL 0x04
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#define CCM_CCTL 0x08
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#define CCM_CGCR0 0x0C
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#define CCM_CGCR1 0x10
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#define CCM_CGCR2 0x14
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#define CCM_PCDR0 0x18
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#define CCM_PCDR1 0x1C
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#define CCM_PCDR2 0x20
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#define CCM_PCDR3 0x24
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#define CCM_RCSR 0x28
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#define CCM_CRDR 0x2C
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#define CCM_DCVR0 0x30
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#define CCM_DCVR1 0x34
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#define CCM_DCVR2 0x38
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#define CCM_DCVR3 0x3c
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#define CCM_LTR0 0x40
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#define CCM_LTR1 0x44
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#define CCM_LTR2 0x48
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#define CCM_LTR3 0x4c
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#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
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#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
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#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
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#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
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#define PDR0_AUTO_CON (1 << 0)
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#define PDR0_PER_SEL (1 << 26)
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/*
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* Adresses and ranges of the external chip select lines
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*/
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#define IMX_CS0_BASE 0xA0000000
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#define IMX_CS0_RANGE (128 * 1024 * 1024)
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#define IMX_CS1_BASE 0xA8000000
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#define IMX_CS1_RANGE (128 * 1024 * 1024)
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#define IMX_CS2_BASE 0xB0000000
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#define IMX_CS2_RANGE (32 * 1024 * 1024)
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#define IMX_CS3_BASE 0xB2000000
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#define IMX_CS3_RANGE (32 * 1024 * 1024)
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#define IMX_CS4_BASE 0xB4000000
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#define IMX_CS4_RANGE (32 * 1024 * 1024)
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#define IMX_CS5_BASE 0xB6000000
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#define IMX_CS5_RANGE (32 * 1024 * 1024)
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#define IMX_SDRAM_CS0 0x80000000
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#define IMX_SDRAM_CS1 0x90000000
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#define WEIM_BASE 0xb8002000
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#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
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#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
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#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
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/*
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* Definitions for the clocksource driver
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*
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* These defines are using the i.MX1/27 notation
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* to reuse the clocksource code for these CPUs
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* on the i.MX35
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*/
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/* Part 1: Registers */
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#define GPT_TCTL 0x00
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#define GPT_TPRER 0x04
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#define GPT_TCMP 0x10
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#define GPT_TCR 0x1c
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#define GPT_TCN 0x24
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#define GPT_TSTAT 0x08
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/* Part 2: Bitfields */
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#define TCTL_SWR (1<<15) /* Software reset */
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#define TCTL_FRR (1<<9) /* Freerun / restart */
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#define TCTL_CAP (3<<6) /* Capture Edge */
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#define TCTL_OM (1<<5) /* output mode */
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#define TCTL_IRQEN (1<<4) /* interrupt enable */
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#define TCTL_CLKSOURCE (6) /* Clock source bit position */
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#define TCTL_TEN (1) /* Timer enable */
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#define TPRER_PRES (0xff) /* Prescale */
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#define TSTAT_CAPT (1<<1) /* Capture event */
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#define TSTAT_COMP (1) /* Compare event */
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/*
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* Watchdog Registers
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*/
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#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
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#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
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#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
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/* important definition of some bits of WCR */
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#define WCR_WDE 0x04
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#endif /* __ASM_ARCH_MX25_REGS_H */
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