313 lines
8.1 KiB
ArmAsm
313 lines
8.1 KiB
ArmAsm
/**
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* @file
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* @brief Provides PRCM divisors and SRAM execution code.
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*
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* FileName: arch/arm/mach-omap/omap3_clock_core.S
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*
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* This provides two things:
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* @li @ref omap3_clock.c cannot have switch or global variables.
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* This file provides the constant data for the file to use.
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*
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* @li @ref prcm_init cannot execute certain critical clock
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* configurations while running in SDRAM/Flash. This provides
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* relocation and execution capability for the same.
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*
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* Orignally from http://linux.omap.com/pub/bootloader/3430sdp/barebox-v1.tar.gz
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*/
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <mach/silicon.h>
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#include <mach/clocks.h>
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#include <mach/gpmc.h>
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#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
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/**
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* @fn void cpy_clk_code(u32 R1)
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*
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* @brief cpy_clk_code: relocates clock code into SRAM where its safer to
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* execute
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*
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* @param[in] R1 = SRAM destination address.
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*
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* @return void
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*/
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.global cpy_clk_code
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cpy_clk_code:
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/* Copy DPLL code into SRAM */
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adr r0, go_to_speed /* get addr of clock setting code */
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mov r2, #384 /* r2 size to copy (div by 32 bytes) */
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mov r1, r1 /* r1 <- dest address (passed in) */
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add r2, r2, r0 /* r2 <- source end address */
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next2:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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bne next2
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mov pc, lr /* back to caller */
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/**
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* @fn void go_to_speed(u32 R0, u32 R1, u32 R3)
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*
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* @brief go_to_speed: Function which configures the clocks
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* Moves to bypass, -Commits clock dividers, -puts dpll at speed
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* -executed from SRAM.
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* @warning Note: If core unlocks/relocks and SDRAM is running fast already
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* it gets confused. A reset of the controller gets it back. Taking
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* away its L3 when its not in self refresh seems bad for it.
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* Normally, this code runs from flash before SDR is init so that
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* should be ok.
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*
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* @param[in] R1 = SRAM destination address.
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* @param[in] R0 = CM_CLKEN_PLL-bypass value
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* @param[in] R1 = CM_CLKSEL1_PLL-m, n, and divider values
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* @param[in] R2 = CM_CLKSEL_CORE-divider values
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* @param[in] R3 = CM_IDLEST_CKGEN - addr dpll lock wait
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*
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* @return void
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*/
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.global go_to_speed
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go_to_speed:
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stmfd sp!, {r4-r6}
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/* move into fast relock bypass */
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ldr r4, pll_ctl_add
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str r0, [r4]
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wait1:
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ldr r5, [r3] /* get status */
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and r5, r5, #0x1 /* isolate core status */
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cmp r5, #0x1 /* still locked? */
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beq wait1 /* if lock, loop */
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/* set new dpll dividers _after_ in bypass */
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ldr r5, pll_div_add1
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str r1, [r5] /* set m, n, m2 */
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ldr r5, pll_div_add2
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str r2, [r5] /* set l3/l4/.. dividers*/
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ldr r5, pll_div_add3 /* wkup */
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ldr r2, pll_div_val3 /* rsm val */
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str r2, [r5]
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ldr r5, pll_div_add4 /* gfx */
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ldr r2, pll_div_val4
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str r2, [r5]
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ldr r5, pll_div_add5 /* emu */
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ldr r2, pll_div_val5
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str r2, [r5]
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#if 0
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/* FIXME: now prepare GPMC (flash) for new dpll speed
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* For NOR/NAND/OneNAND boot ->make this as Kconfig?
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*/
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/* flash needs to be stable when we jump back to it */
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ldr r6, flash_cfg_offset
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ldr r5, flash_cfg_addr /* CFG1 */
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ldr r2, flash_cfg1_val
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str r2, [r5]
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add r5, r5, r6 /* CFG2 */
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ldr r2, flash_cfg2_val
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str r2, [r5]
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add r5, r5, r6 /* CFG3 */
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ldr r2, flash_cfg3_val
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str r2, [r5]
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add r5, r5, r6 /* CFG4 */
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ldr r2, flash_cfg4_val
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str r2, [r5]
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add r5, r5, r6 /* CFG5 */
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ldr r2, flash_cfg5_val
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str r2, [r5]
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add r5, r5, r6 /* CFG6 */
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ldr r2, flash_cfg6_val
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str r2, [r5]
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#endif /* Debug */
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/* lock DPLL3 and wait a bit */
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orr r0, r0, #0x7 /* set up for lock mode */
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str r0, [r4] /* lock */
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nop /* ARM slow at this point working at sys_clk */
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nop
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nop
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nop
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wait2:
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ldr r5, [r3] /* get status */
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and r5, r5, #0x1 /* isolate core status */
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cmp r5, #0x1 /* still locked? */
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bne wait2 /* if lock, loop */
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nop
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nop
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nop
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nop
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ldmfd sp!, {r4-r6}
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mov pc, lr /* back to caller, locked */
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_go_to_speed: .word go_to_speed
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/* these constants need to be close for PIC code */
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/* FIXME: The Nor has to be in the Flash Base CS0 for this condition to happen*/
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#if 0
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flash_cfg_addr:
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.word GPMC_REG(CONFIG1_0)
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flash_cfg_offset:
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.word GPMC_REG(CONFIG2_0) - GPMC_REG(CONFIG1_0)
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flash_cfg1_val:
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.word CONFIG_VALUE_GPMC_CONFIG1
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flash_cfg2_val:
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.word CONFIG_VALUE_GPMC_CONFIG2
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flash_cfg3_val:
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.word CONFIG_VALUE_GPMC_CONFIG3
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flash_cfg4_val:
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.word CONFIG_VALUE_GPMC_CONFIG4
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flash_cfg5_val:
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.word CONFIG_VALUE_GPMC_CONFIG5
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flash_cfg6_val:
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.word CONFIG_VALUE_GPMC_CONFIG6
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#endif
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pll_ctl_add:
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.word CM_CLKEN_PLL
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pll_div_add1:
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.word CM_CLKSEL1_PLL
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pll_div_add2:
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.word CM_CLKSEL_CORE
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pll_div_add3:
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.word CM_CLKSEL_WKUP
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pll_div_val3:
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.word (WKUP_RSM << 1)
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pll_div_add4:
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.word CM_CLKSEL_GFX
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pll_div_val4:
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.word (GFX_DIV << 0)
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pll_div_add5:
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.word CM_CLKSEL1_EMU
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pll_div_val5:
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.word CLSEL1_EMU_VAL
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#endif /* OMAP3_CLOCK_COPY_SRAM */
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/* the literal pools origin */
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.ltorg
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/* DPLL(1-4) PARAM TABLES */
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/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
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* OPP (1.2V). The fields are defined according to dpll_param
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* struct(omap3_clock.c). MAX index is as per omap3_clock.h
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*/
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mpu_dpll_param:
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/* 12MHz */
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/* ES2 */
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.word 0x0FA,0x05,0x07,0x01
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/* 13MHz */
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/* ES2 */
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.word 0x1F4,0x0C,0x03,0x01
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/* 19.2MHz */
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/* ES2 */
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.word 0x271,0x17,0x03,0x01
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/* 26MHz */
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/* ES2 */
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.word 0x0FA,0x0C,0x07,0x01
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/* 38.4MHz */
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/* ES2 */
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.word 0x271,0x2F,0x03,0x01
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.globl get_mpu_dpll_param
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get_mpu_dpll_param:
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adr r0, mpu_dpll_param
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mov pc, lr
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iva_dpll_param:
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/* 12MHz */
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/* ES2 */
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.word 0x0B4,0x05,0x07,0x01
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/* 13MHz */
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/* ES2 */
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.word 0x168,0x0C,0x03,0x01
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/* 19.2MHz */
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/* ES2 */
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.word 0x0E1,0x0B,0x06,0x01
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/* 26MHz */
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/* ES2 */
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.word 0x0B4,0x0C,0x07,0x01
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/* 38.4MHz */
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/* ES2 */
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.word 0x0E1,0x17,0x06,0x01
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.globl get_iva_dpll_param
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get_iva_dpll_param:
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adr r0, iva_dpll_param
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mov pc, lr
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core_dpll_param:
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/* 12MHz */
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/* ES2 */
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.word 0x0A6,0x05,0x07,0x01
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/* 13MHz */
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/* ES2 */
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.word 0x14C,0x0C,0x03,0x01
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/* 19.2MHz */
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/* ES2 */
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.word 0x19F,0x17,0x03,0x01
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/* 26MHz */
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/* ES2 */
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.word 0x0A6,0x0C,0x07,0x01
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/* 38.4MHz */
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/* ES2 */
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.word 0x19F,0x2F,0x03,0x01
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.globl get_core_dpll_param
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get_core_dpll_param:
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adr r0, core_dpll_param
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mov pc, lr
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/* PER DPLL values are same for both ES1 and ES2 */
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per_dpll_param:
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/* 12MHz */
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.word 0xD8,0x05,0x07,0x09
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/* 13MHz */
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.word 0x1B0,0x0C,0x03,0x09
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/* 19.2MHz */
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.word 0xE1,0x09,0x07,0x09
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/* 26MHz */
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.word 0xD8,0x0C,0x07,0x09
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/* 38.4MHz */
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.word 0xE1,0x13,0x07,0x09
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.globl get_per_dpll_param
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get_per_dpll_param:
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adr r0, per_dpll_param
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mov pc, lr
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