102 lines
3.5 KiB
ArmAsm
102 lines
3.5 KiB
ArmAsm
/**
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* @file
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* @brief Provide Architecture level Initialization
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*
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* FileName: arch/arm/mach-omap/omap3_core.S
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*
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* This provides OMAP3 Architecture initialization. Among these,
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* @li OMAP ROM Code is located in SRAM, we can piggy back on
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* the same addresses
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* @li If clock initialization is required, call the same.
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* @li Setup a temporary SRAM stack which is necessary to call C
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* functions.
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* @li Call architecture initialization function a_init
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*
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* arch_init_lowlevel is enabled if CONFIG_ARCH_HAS_LOWLEVEL_INIT is defined
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* cpy_clk_code is called if CONFIG_OMAP3_COPY_CLOCK_SRAM is defined
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*/
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <mach/silicon.h>
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#include <mach/wdt.h>
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#include <mach/clocks.h>
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#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
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.globl arch_init_lowlevel
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arch_init_lowlevel:
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/* Copy vectors to mask ROM indirect addr */
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mov r0, pc /* Store the current pc address */
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sub r0, r0, #8 /* Reduce offset */
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ldr r1, arch_start /* Load the link address for arch_int */
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ldr r2, barebox_start /* load the link address of start_init*/
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sub r1, r1, r2 /* get the offset */
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/* subtract the offset from PC of arch=Current start */
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sub r0, r0, r1
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mov r2, #OMAP_SRAM_INTVECT_COPYSIZE /* r2 <- size to copy */
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add r2, r0, r2 /* r2 <- source end address */
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ldr r1, SRAM_INTVECT /* build vect addr */
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next:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble next /* loop until equal */
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#ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM
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/* No need to copy/exec the clock code - DPLL adjust already done
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* in Perip/NAND/oneNAND Boot.
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* Put dpll adjust code behind vectors. r1 has address to copy to
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*/
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bl cpy_clk_code
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#endif
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ldr r1, SRAM_INTVECT /* build vect addr */
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/* Read the interrupt vector base address */
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mrc p15, #0, r0, c12, c0, #0
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/* Clear the vector base 4:0 is reserved. */
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and r0, r0, #0xF
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/* Store the SRAM_INTVECT address */
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orr r0, r0, r1
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/* Store the new vector address */
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mcr p15, #0, r0, c12, c0, #0
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/* Setup a temporary stack so that we can call C functions */
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash old link register */
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str lr, [sp] /* stash current link register */
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mov ip, lr /* save link reg across call */
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bl a_init /* Architecture init */
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ldr lr, [sp] /* restore current link register */
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ldr ip, [sp] /* restore save ip */
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/* back to arch calling code */
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mov pc, lr
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arch_start:
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.word arch_init_lowlevel
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barebox_start:
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.word _start
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SRAM_INTVECT:
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.word OMAP_SRAM_INTVECT
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SRAM_STACK:
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.word OMAP_SRAM_STACK
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#endif /* CONFIG_ARCH_HAS_LOWLEVEL_INIT */
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