437 lines
11 KiB
C
437 lines
11 KiB
C
/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Designware ethernet IP driver for u-boot
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <net.h>
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#include <miidev.h>
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#include <asm/mmu.h>
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#include <net/designware.h>
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#include "designware.h"
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struct dw_eth_dev {
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struct eth_device netdev;
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struct mii_device miidev;
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void (*fix_mac_speed)(int speed);
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u8 macaddr[6];
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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struct dmamacdescr *tx_mac_descrtable;
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struct dmamacdescr *rx_mac_descrtable;
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u8 *txbuffs;
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u8 *rxbuffs;
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struct eth_mac_regs *mac_regs_p;
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struct eth_dma_regs *dma_regs_p;
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};
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/* Speed specific definitions */
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#define SPEED_10M 1
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#define SPEED_100M 2
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#define SPEED_1000M 3
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/* Duplex mode specific definitions */
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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static int dwc_ether_mii_read(struct mii_device *dev, int addr, int reg)
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{
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struct dw_eth_dev *priv = dev->edev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u64 start;
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u32 miiaddr;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_time_ns();
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while (readl(&mac_p->miiaddr) & MII_BUSY) {
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if (is_timeout(start, 10 * MSECOND)) {
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dev_err(&priv->netdev.dev, "MDIO timeout\n");
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return -EIO;
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}
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}
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return readl(&mac_p->miidata) & 0xffff;
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}
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static int dwc_ether_mii_write(struct mii_device *dev, int addr, int reg, int val)
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{
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struct dw_eth_dev *priv = dev->edev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u64 start;
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u32 miiaddr;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_time_ns();
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while (readl(&mac_p->miiaddr) & MII_BUSY) {
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if (is_timeout(start, 10 * MSECOND)) {
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dev_err(&priv->netdev.dev, "MDIO timeout\n");
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return -EIO;
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}
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}
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/* Needed as a fix for ST-Phy */
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dwc_ether_mii_read(dev, addr, reg);
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return 0;
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}
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static int mac_reset(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u64 start;
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writel(DMAMAC_SRST, &dma_p->busmode);
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writel(MII_PORTSELECT, &mac_p->conf);
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start = get_time_ns();
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while (readl(&dma_p->busmode) & DMAMAC_SRST) {
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if (is_timeout(start, 10 * MSECOND)) {
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dev_err(&priv->netdev.dev, "MAC reset timeout\n");
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return -EIO;
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}
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}
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return 0;
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}
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static void tx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
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char *txbuffs = &priv->txbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
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DESC_TXSTS_TXCHECKINSCTRL | \
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DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
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desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
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desc_p->dmamac_cntl = 0;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
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#else
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desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
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desc_p->txrx_status = 0;
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#endif
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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}
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static void rx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
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char *rxbuffs = &priv->rxbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
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DESC_RXCTRL_RXCHAIN;
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dma_inv_range((unsigned long)desc_p->dmamac_addr,
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(unsigned long)desc_p->dmamac_addr + CONFIG_ETH_BUFSIZE);
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desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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}
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static void descs_init(struct eth_device *dev)
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{
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tx_descs_init(dev);
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rx_descs_init(dev);
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}
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static int dwc_ether_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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if (mac_reset(dev) < 0)
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return -1;
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/* HW MAC address is lost during MAC reset */
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dev->set_ethaddr(dev, priv->macaddr);
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
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writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
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writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
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writel(FRAMEBURSTENABLE | DISABLERXOWN, &mac_p->conf);
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return 0;
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}
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static int dwc_ether_open(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 conf;
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int link, speed;
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miidev_wait_aneg(&priv->miidev);
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miidev_print_status(&priv->miidev);
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link = miidev_get_status(&priv->miidev);
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if (priv->fix_mac_speed) {
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speed = link & MIIDEV_STATUS_IS_1000MBIT ? 1000 :
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(link & MIIDEV_STATUS_IS_100MBIT ? 100 : 10);
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priv->fix_mac_speed(speed);
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}
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conf = readl(&mac_p->conf);
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if (link & MIIDEV_STATUS_IS_FULL_DUPLEX)
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conf |= FULLDPLXMODE;
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else
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conf &= ~FULLDPLXMODE;
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if (link & MIIDEV_STATUS_IS_1000MBIT)
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conf &= ~MII_PORTSELECT;
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else
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conf |= MII_PORTSELECT;
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writel(conf, &mac_p->conf);
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descs_init(dev);
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/*
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* Start/Enable xfer at dma as well as mac level
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*/
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writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
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writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
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writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
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return 0;
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}
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static int dwc_ether_send(struct eth_device *dev, void *packet, int length)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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/* Check if the descriptor is owned by CPU */
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if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
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dev_err(&dev->dev, "CPU not owner of tx frame\n");
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return -1;
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}
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memcpy((void *)desc_p->dmamac_addr, packet, length);
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dma_flush_range((unsigned long)desc_p->dmamac_addr,
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(unsigned long)desc_p->dmamac_addr + length);
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#if defined(CONFIG_DRIVER_NET_DESIGNWARE_ALTDESCRIPTOR)
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desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
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desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
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desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
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#else
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desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
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DESC_TXCTRL_TXFIRST;
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desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
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#endif
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_TX_DESCR_NUM)
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desc_num = 0;
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priv->tx_currdescnum = desc_num;
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/* Start the transmission */
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writel(POLL_DATA, &dma_p->txpolldemand);
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return 0;
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}
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static int dwc_ether_rx(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u32 desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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u32 status = desc_p->txrx_status;
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int length = 0;
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/* Check if the owner is the CPU */
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if (status & DESC_RXSTS_OWNBYDMA)
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return 0;
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length = (status & DESC_RXSTS_FRMLENMSK) >> \
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DESC_RXSTS_FRMLENSHFT;
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net_receive(desc_p->dmamac_addr, length);
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/*
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* Make the current descriptor valid again and go to
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* the next one
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*/
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dma_inv_range((unsigned long)desc_p->dmamac_addr,
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(unsigned long)desc_p->dmamac_addr + length);
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desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_RX_DESCR_NUM)
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desc_num = 0;
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priv->rx_currdescnum = desc_num;
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return length;
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}
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static void dwc_ether_halt (struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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mac_reset(dev);
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priv->tx_currdescnum = priv->rx_currdescnum = 0;
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}
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static int dwc_ether_get_ethaddr(struct eth_device *dev, u8 adr[6])
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{
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/* we have no EEPROM */
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return -1;
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}
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static int dwc_ether_set_ethaddr(struct eth_device *dev, u8 adr[6])
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 macid_lo, macid_hi;
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macid_lo = adr[0] + (adr[1] << 8) + \
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(adr[2] << 16) + (adr[3] << 24);
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macid_hi = adr[4] + (adr[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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writel(macid_lo, &mac_p->macaddr0lo);
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memcpy(priv->macaddr, adr, 6);
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return 0;
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}
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static int dwc_ether_probe(struct device_d *dev)
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{
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struct dw_eth_dev *priv;
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struct eth_device *edev;
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struct mii_device *miidev;
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void __iomem *base;
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struct dwc_ether_platform_data *pdata = dev->platform_data;
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if (!pdata) {
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printf("dwc_ether: no platform_data\n");
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return -ENODEV;
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}
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priv = xzalloc(sizeof(struct dw_eth_dev));
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base = dev_request_mem_region(dev, 0);
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priv->mac_regs_p = base;
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dev_info(dev, "MAC version %08x\n", readl(&priv->mac_regs_p->version));
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priv->dma_regs_p = base + DW_DMA_BASE_OFFSET;
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priv->tx_mac_descrtable = dma_alloc_coherent(
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CONFIG_TX_DESCR_NUM * sizeof(struct dmamacdescr));
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priv->rx_mac_descrtable = dma_alloc_coherent(
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CONFIG_RX_DESCR_NUM * sizeof(struct dmamacdescr));
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priv->txbuffs = malloc(TX_TOTAL_BUFSIZE);
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priv->rxbuffs = malloc(RX_TOTAL_BUFSIZE);
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priv->fix_mac_speed = pdata->fix_mac_speed;
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edev = &priv->netdev;
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miidev = &priv->miidev;
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edev->priv = priv;
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edev->init = dwc_ether_init;
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edev->open = dwc_ether_open;
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edev->send = dwc_ether_send;
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edev->recv = dwc_ether_rx;
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edev->halt = dwc_ether_halt;
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edev->get_ethaddr = dwc_ether_get_ethaddr;
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edev->set_ethaddr = dwc_ether_set_ethaddr;
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miidev->address = pdata->phy_addr;
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miidev->read = dwc_ether_mii_read;
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miidev->write = dwc_ether_mii_write;
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miidev->edev = edev;
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mii_register(miidev);
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eth_register(edev);
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return 0;
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}
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static void dwc_ether_remove(struct device_d *dev)
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{
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}
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static struct driver_d dwc_ether_driver = {
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.name = "designware_eth",
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.probe = dwc_ether_probe,
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.remove = dwc_ether_remove,
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};
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static int dwc_ether_driver_init(void)
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{
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register_driver(&dwc_ether_driver);
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return 0;
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}
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device_initcall(dwc_ether_driver_init);
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