612 lines
19 KiB
C
612 lines
19 KiB
C
/*
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* Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de>
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*
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* Ethernet driver for TI TMS320DM644x (DaVinci) chips.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
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* follows:
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*
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* ----------------------------------------------------------------------------
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*
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* dm644x_emac.c
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*
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* TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
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*
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* Copyright (C) 2005 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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* Modifications:
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* ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
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* ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <clock.h>
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#include <net.h>
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#include <malloc.h>
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#include <init.h>
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#include <asm/mmu.h>
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#include <asm/system.h>
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#include <linux/phy.h>
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#include <mach/emac_defs.h>
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#include <net/davinci_emac.h>
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#include "davinci_emac.h"
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struct davinci_emac_priv {
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struct device_d *dev;
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struct eth_device edev;
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struct mii_bus miibus;
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/* EMAC Addresses */
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void __iomem *adap_emac; /* = EMAC_BASE_ADDR */
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void __iomem *adap_ewrap; /* = EMAC_WRAPPER_BASE_ADDR */
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void __iomem *adap_mdio; /* = EMAC_MDIO_BASE_ADDR */
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/* EMAC descriptors */
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void __iomem *emac_desc_base; /* = EMAC_WRAPPER_RAM_ADDR */
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void __iomem *emac_rx_desc; /* = EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE */
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void __iomem *emac_tx_desc; /* = EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE */
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void __iomem *emac_rx_active_head; /* = 0 */
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void __iomem *emac_rx_active_tail; /* = 0 */
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int emac_rx_queue_active; /* = 0 */
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/* Receive packet buffers */
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unsigned char *emac_rx_buffers; /* [EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)] */
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/* PHY-specific information */
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phy_interface_t interface;
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uint8_t phy_addr;
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uint32_t phy_flags;
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/* mac_addr[0] goes out on the wire first */
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uint8_t mac_addr[6];
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};
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#ifdef EMAC_HW_RAM_ADDR
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static inline uint32_t BD_TO_HW(void __iomem *x)
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{
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if (x == 0)
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return 0;
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return (uint32_t)(x) - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
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}
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static inline void __iomem *HW_TO_BD(uint32_t x)
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{
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if (x == 0)
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return 0;
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return (struct emac_desc*)(x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR);
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}
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#else
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#define BD_TO_HW(x) (x)
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#define HW_TO_BD(x) (x)
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#endif
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static void davinci_eth_mdio_enable(struct davinci_emac_priv *priv)
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{
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uint32_t clkdiv;
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clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
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dev_dbg(priv->dev, "mdio_enable + 0x%08x\n",
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readl(priv->adap_mdio + EMAC_MDIO_CONTROL));
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writel((clkdiv & 0xff) |
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MDIO_CONTROL_ENABLE |
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MDIO_CONTROL_FAULT |
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MDIO_CONTROL_FAULT_ENABLE,
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priv->adap_mdio + EMAC_MDIO_CONTROL);
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dev_dbg(priv->dev, "mdio_enable - 0x%08x\n",
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readl(priv->adap_mdio + EMAC_MDIO_CONTROL));
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while (readl(priv->adap_mdio + EMAC_MDIO_CONTROL) & MDIO_CONTROL_IDLE);
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}
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static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
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{
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struct davinci_emac_priv *priv = bus->priv;
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uint16_t value;
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int tmp;
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while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
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writel(MDIO_USERACCESS0_GO |
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MDIO_USERACCESS0_WRITE_READ |
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((reg & 0x1f) << 21) |
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((addr & 0x1f) << 16),
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priv->adap_mdio + EMAC_MDIO_USERACCESS0);
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/* Wait for command to complete */
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while ((tmp = readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0)) & MDIO_USERACCESS0_GO);
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if (tmp & MDIO_USERACCESS0_ACK) {
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value = tmp & 0xffff;
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dev_dbg(priv->dev, "davinci_miibus_read: addr=0x%02x reg=0x%02x value=0x%04x\n",
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addr, reg, value);
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return value;
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}
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return -1;
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}
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static int davinci_miibus_write(struct mii_bus *bus, int addr, int reg, u16 value)
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{
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struct davinci_emac_priv *priv = bus->priv;
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while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
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dev_dbg(priv->dev, "davinci_miibus_write: addr=0x%02x reg=0x%02x value=0x%04x\n",
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addr, reg, value);
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writel(MDIO_USERACCESS0_GO |
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MDIO_USERACCESS0_WRITE_WRITE |
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((reg & 0x1f) << 21) |
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((addr & 0x1f) << 16) |
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(value & 0xffff),
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priv->adap_mdio + EMAC_MDIO_USERACCESS0);
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/* Wait for command to complete */
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while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
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return 0;
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}
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static int davinci_emac_get_ethaddr(struct eth_device *edev, unsigned char *adr)
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{
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return -1;
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}
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/*
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* This function must be called before emac_open() if you want to override
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* the default mac address.
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*/
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static int davinci_emac_set_ethaddr(struct eth_device *edev, unsigned char *addr)
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{
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struct davinci_emac_priv *priv = edev->priv;
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int i;
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for (i = 0; i < sizeof(priv->mac_addr); i++)
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priv->mac_addr[i] = addr[i];
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return 0;
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}
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static int davinci_emac_init(struct eth_device *edev)
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{
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dev_dbg(&edev->dev, "* emac_init\n");
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return 0;
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}
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static int davinci_emac_open(struct eth_device *edev)
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{
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struct davinci_emac_priv *priv = edev->priv;
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uint32_t clkdiv, cnt;
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void __iomem *rx_desc;
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unsigned long mac_hi, mac_lo;
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int ret;
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dev_dbg(priv->dev, "+ emac_open\n");
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dev_dbg(priv->dev, "emac->TXIDVER: 0x%08x\n",
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readl(priv->adap_emac + EMAC_TXIDVER));
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dev_dbg(priv->dev, "emac->RXIDVER: 0x%08x\n",
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readl(priv->adap_emac + EMAC_RXIDVER));
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/* Reset EMAC module and disable interrupts in wrapper */
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writel(1, priv->adap_emac + EMAC_SOFTRESET);
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while (readl(priv->adap_emac + EMAC_SOFTRESET) != 0);
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writel(1, priv->adap_ewrap + EMAC_EWRAP_SOFTRESET);
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while (readl(priv->adap_ewrap + EMAC_EWRAP_SOFTRESET) != 0);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0MISCEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1MISCEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2MISCEN);
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rx_desc = priv->emac_rx_desc;
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/*
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* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
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* receive)
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* Use channel 0 only - other channels are disabled
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*/
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writel(0, priv->adap_emac + EMAC_MACINDEX);
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mac_hi = (priv->mac_addr[3] << 24) |
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(priv->mac_addr[2] << 16) |
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(priv->mac_addr[1] << 8) |
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(priv->mac_addr[0]);
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mac_lo = (priv->mac_addr[5] << 8) |
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(priv->mac_addr[4]);
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writel(mac_hi, priv->adap_emac + EMAC_MACADDRHI);
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writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
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priv->adap_emac + EMAC_MACADDRLO);
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/* Set source MAC address - REQUIRED */
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writel(mac_hi, priv->adap_emac + EMAC_MACSRCADDRHI);
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writel(mac_lo, priv->adap_emac + EMAC_MACSRCADDRLO);
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/* Set DMA head and completion pointers to 0 */
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for(cnt = 0; cnt < 8; cnt++) {
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writel(0, (void *)priv->adap_emac + EMAC_TX0HDP + 4 * cnt);
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writel(0, (void *)priv->adap_emac + EMAC_RX0HDP + 4 * cnt);
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writel(0, (void *)priv->adap_emac + EMAC_TX0CP + 4 * cnt);
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writel(0, (void *)priv->adap_emac + EMAC_RX0CP + 4 * cnt);
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}
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/* Clear Statistics (do this before setting MacControl register) */
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for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
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writel(0, (void *)priv->adap_emac + EMAC_RXGOODFRAMES + 4 * cnt);
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/* No multicast addressing */
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writel(0, priv->adap_emac + EMAC_MACHASH1);
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writel(0, priv->adap_emac + EMAC_MACHASH2);
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writel(0x01, priv->adap_emac + EMAC_TXCONTROL);
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writel(0x01, priv->adap_emac + EMAC_RXCONTROL);
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/* Create RX queue and set receive process in place */
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priv->emac_rx_active_head = priv->emac_rx_desc;
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for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
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writel(BD_TO_HW(rx_desc + EMAC_DESC_SIZE), rx_desc + EMAC_DESC_NEXT);
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writel(&priv->emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)], rx_desc + EMAC_DESC_BUFFER);
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writel(EMAC_MAX_ETHERNET_PKT_SIZE, rx_desc + EMAC_DESC_BUFF_OFF_LEN);
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writel(EMAC_CPPI_OWNERSHIP_BIT, rx_desc + EMAC_DESC_PKT_FLAG_LEN);
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rx_desc += EMAC_DESC_SIZE;
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}
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/* Set the last descriptor's "next" parameter to 0 to end the RX desc list */
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rx_desc -= EMAC_DESC_SIZE;
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writel(0, rx_desc + EMAC_DESC_NEXT);
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priv->emac_rx_active_tail = rx_desc;
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priv->emac_rx_queue_active = 1;
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/* Enable TX/RX */
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writel(EMAC_MAX_ETHERNET_PKT_SIZE, priv->adap_emac + EMAC_RXMAXLEN);
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writel(0, priv->adap_emac + EMAC_RXBUFFEROFFSET);
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/* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */
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writel(EMAC_RXMBPENABLE_RXBROADEN, priv->adap_emac + EMAC_RXMBPENABLE);
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/* Enable ch 0 only */
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writel(0x01, priv->adap_emac + EMAC_RXUNICASTSET);
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/* Enable MII interface and full duplex mode (using RMMI) */
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writel((EMAC_MACCONTROL_MIIEN_ENABLE |
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EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
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EMAC_MACCONTROL_RMIISPEED_100),
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priv->adap_emac + EMAC_MACCONTROL);
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/* Init MDIO & get link state */
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clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
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writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
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priv->adap_mdio + EMAC_MDIO_CONTROL);
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/* Start receive process */
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writel(BD_TO_HW(priv->emac_rx_desc), priv->adap_emac + EMAC_RX0HDP);
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ret = phy_device_connect(edev, &priv->miibus, priv->phy_addr, NULL,
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priv->phy_flags, priv->interface);
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if (ret)
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return ret;
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dev_dbg(priv->dev, "- emac_open\n");
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return 0;
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}
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/* EMAC Channel Teardown */
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static void davinci_eth_ch_teardown(struct davinci_emac_priv *priv, int ch)
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{
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uint32_t dly = 0xff;
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uint32_t cnt;
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dev_dbg(priv->dev, "+ emac_ch_teardown\n");
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if (ch == EMAC_CH_TX) {
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/* Init TX channel teardown */
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writel(0, priv->adap_emac + EMAC_TXTEARDOWN);
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for(cnt = 0; cnt != 0xfffffffc; cnt = readl(priv->adap_emac + EMAC_TX0CP)) {
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/* Wait here for Tx teardown completion interrupt to occur
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* Note: A task delay can be called here to pend rather than
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* occupying CPU cycles - anyway it has been found that teardown
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* takes very few cpu cycles and does not affect functionality */
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dly--;
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udelay(1);
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if (dly == 0)
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break;
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}
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writel(cnt, priv->adap_emac + EMAC_TX0CP);
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writel(0, priv->adap_emac + EMAC_TX0HDP);
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} else {
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/* Init RX channel teardown */
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writel(0, priv->adap_emac + EMAC_RXTEARDOWN);
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for(cnt = 0; cnt != 0xfffffffc; cnt = readl(priv->adap_emac + EMAC_RX0CP)) {
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/* Wait here for Rx teardown completion interrupt to occur
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* Note: A task delay can be called here to pend rather than
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* occupying CPU cycles - anyway it has been found that teardown
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* takes very few cpu cycles and does not affect functionality */
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dly--;
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udelay(1);
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if (dly == 0)
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break;
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}
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writel(cnt, priv->adap_emac + EMAC_RX0CP);
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writel(0, priv->adap_emac + EMAC_RX0HDP);
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}
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dev_dbg(priv->dev, "- emac_ch_teardown\n");
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}
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static void davinci_emac_halt(struct eth_device *edev)
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{
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struct davinci_emac_priv *priv = edev->priv;
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dev_dbg(priv->dev, "+ emac_halt\n");
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davinci_eth_ch_teardown(priv, EMAC_CH_TX); /* TX Channel teardown */
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davinci_eth_ch_teardown(priv, EMAC_CH_RX); /* RX Channel teardown */
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/* Reset EMAC module and disable interrupts in wrapper */
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writel(1, priv->adap_emac + EMAC_SOFTRESET);
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writel(1, priv->adap_ewrap + EMAC_EWRAP_SOFTRESET);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2RXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2TXEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C0MISCEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C1MISCEN);
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writel(0, priv->adap_ewrap + EMAC_EWRAP_C2MISCEN);
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dev_dbg(priv->dev, "- emac_halt\n");
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}
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/*
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* This function sends a single packet on the network
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* and returns 0 on successful transmit or negative for error
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*/
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static int davinci_emac_send(struct eth_device *edev, void *packet, int length)
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{
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struct davinci_emac_priv *priv = edev->priv;
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uint64_t start;
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int ret_status;
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dev_dbg(priv->dev, "+ emac_send (length %d)\n", length);
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/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
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if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
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length = EMAC_MIN_ETHERNET_PKT_SIZE;
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}
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/* Populate the TX descriptor */
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writel(0, priv->emac_tx_desc + EMAC_DESC_NEXT);
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writel((uint8_t *) packet, priv->emac_tx_desc + EMAC_DESC_BUFFER);
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writel((length & 0xffff), priv->emac_tx_desc + EMAC_DESC_BUFF_OFF_LEN);
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writel(((length & 0xffff) | EMAC_CPPI_SOP_BIT |
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EMAC_CPPI_OWNERSHIP_BIT |
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EMAC_CPPI_EOP_BIT),
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priv->emac_tx_desc + EMAC_DESC_PKT_FLAG_LEN);
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dma_flush_range((ulong) packet, (ulong)packet + length);
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/* Send the packet */
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writel(BD_TO_HW(priv->emac_tx_desc), priv->adap_emac + EMAC_TX0HDP);
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/* Wait for packet to complete or link down */
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start = get_time_ns();
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while (1) {
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if (readl(priv->adap_emac + EMAC_TXINTSTATRAW) & 0x01) {
|
|
/* Acknowledge the TX descriptor */
|
|
writel(BD_TO_HW(priv->emac_tx_desc), priv->adap_emac + EMAC_TX0CP);
|
|
ret_status = 0;
|
|
break;
|
|
}
|
|
if (is_timeout(start, 100 * MSECOND)) {
|
|
ret_status = -ETIMEDOUT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
dev_dbg(priv->dev, "- emac_send (ret_status %i)\n", ret_status);
|
|
return ret_status;
|
|
}
|
|
|
|
/*
|
|
* This function handles receipt of a packet from the network
|
|
*/
|
|
static int davinci_emac_recv(struct eth_device *edev)
|
|
{
|
|
struct davinci_emac_priv *priv = edev->priv;
|
|
void __iomem *rx_curr_desc, *curr_desc, *tail_desc;
|
|
unsigned char *pkt;
|
|
int status, len, ret = -1;
|
|
|
|
dev_dbg(priv->dev, "+ emac_recv\n");
|
|
|
|
rx_curr_desc = priv->emac_rx_active_head;
|
|
status = readl(rx_curr_desc + EMAC_DESC_PKT_FLAG_LEN);
|
|
if (status & EMAC_CPPI_OWNERSHIP_BIT) {
|
|
ret = 0;
|
|
goto out;
|
|
}
|
|
|
|
if (status & EMAC_CPPI_RX_ERROR_FRAME) {
|
|
/* Error in packet - discard it and requeue desc */
|
|
dev_warn(priv->dev, "WARN: emac_rcv_pkt: Error in packet\n");
|
|
} else {
|
|
pkt = (unsigned char *)readl(rx_curr_desc + EMAC_DESC_BUFFER);
|
|
len = readl(rx_curr_desc + EMAC_DESC_BUFF_OFF_LEN) & 0xffff;
|
|
dev_dbg(priv->dev, "| emac_recv got packet (length %i)\n", len);
|
|
dma_inv_range((ulong)pkt,
|
|
(ulong)readl(rx_curr_desc + EMAC_DESC_BUFFER) + len);
|
|
net_receive(edev, pkt, len);
|
|
ret = len;
|
|
}
|
|
|
|
/* Ack received packet descriptor */
|
|
writel(BD_TO_HW(rx_curr_desc), priv->adap_emac + EMAC_RX0CP);
|
|
curr_desc = rx_curr_desc;
|
|
priv->emac_rx_active_head = HW_TO_BD(readl(rx_curr_desc + EMAC_DESC_NEXT));
|
|
|
|
if (status & EMAC_CPPI_EOQ_BIT) {
|
|
if (priv->emac_rx_active_head) {
|
|
writel(BD_TO_HW(priv->emac_rx_active_head),
|
|
priv->adap_emac + EMAC_RX0HDP);
|
|
} else {
|
|
priv->emac_rx_queue_active = 0;
|
|
dev_info(priv->dev, "INFO:emac_rcv_packet: RX Queue not active\n");
|
|
}
|
|
}
|
|
|
|
/* Recycle RX descriptor */
|
|
writel(EMAC_MAX_ETHERNET_PKT_SIZE, rx_curr_desc + EMAC_DESC_BUFF_OFF_LEN);
|
|
writel(EMAC_CPPI_OWNERSHIP_BIT, rx_curr_desc + EMAC_DESC_PKT_FLAG_LEN);
|
|
writel(0, rx_curr_desc + EMAC_DESC_NEXT);
|
|
|
|
if (priv->emac_rx_active_head == 0) {
|
|
dev_info(priv->dev, "INFO: emac_rcv_pkt: active queue head = 0\n");
|
|
priv->emac_rx_active_head = curr_desc;
|
|
priv->emac_rx_active_tail = curr_desc;
|
|
if (priv->emac_rx_queue_active != 0) {
|
|
writel(BD_TO_HW(priv->emac_rx_active_head), priv->adap_emac + EMAC_RX0HDP);
|
|
dev_info(priv->dev, "INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
|
|
priv->emac_rx_queue_active = 1;
|
|
}
|
|
} else {
|
|
tail_desc = priv->emac_rx_active_tail;
|
|
priv->emac_rx_active_tail = curr_desc;
|
|
writel(BD_TO_HW(curr_desc), tail_desc + EMAC_DESC_NEXT);
|
|
status = readl(tail_desc + EMAC_DESC_PKT_FLAG_LEN);
|
|
if (status & EMAC_CPPI_EOQ_BIT) {
|
|
writel(BD_TO_HW(curr_desc), priv->adap_emac + EMAC_RX0HDP);
|
|
status &= ~EMAC_CPPI_EOQ_BIT;
|
|
writel(status, tail_desc + EMAC_DESC_PKT_FLAG_LEN);
|
|
}
|
|
}
|
|
|
|
out:
|
|
dev_dbg(priv->dev, "- emac_recv\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int davinci_emac_probe(struct device_d *dev)
|
|
{
|
|
struct davinci_emac_platform_data *pdata;
|
|
struct davinci_emac_priv *priv;
|
|
uint64_t start;
|
|
uint32_t phy_mask;
|
|
|
|
dev_dbg(dev, "+ emac_probe\n");
|
|
|
|
if (!dev->platform_data) {
|
|
dev_err(dev, "no platform_data\n");
|
|
return -ENODEV;
|
|
}
|
|
pdata = dev->platform_data;
|
|
|
|
priv = xzalloc(sizeof(*priv));
|
|
dev->priv = priv;
|
|
|
|
priv->dev = dev;
|
|
|
|
priv->adap_emac = dev_request_mem_region(dev, 0);
|
|
priv->adap_ewrap = dev_request_mem_region(dev, 1);
|
|
priv->adap_mdio = dev_request_mem_region(dev, 2);
|
|
priv->emac_desc_base = dev_request_mem_region(dev, 3);
|
|
|
|
/* EMAC descriptors */
|
|
priv->emac_rx_desc = priv->emac_desc_base + EMAC_RX_DESC_BASE;
|
|
priv->emac_tx_desc = priv->emac_desc_base + EMAC_TX_DESC_BASE;
|
|
priv->emac_rx_active_head = NULL;
|
|
priv->emac_rx_active_tail = NULL;
|
|
priv->emac_rx_queue_active = 0;
|
|
|
|
/* Receive packet buffers */
|
|
priv->emac_rx_buffers = xmemalign(4096, EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN));
|
|
|
|
priv->edev.priv = priv;
|
|
priv->edev.init = davinci_emac_init;
|
|
priv->edev.open = davinci_emac_open;
|
|
priv->edev.halt = davinci_emac_halt;
|
|
priv->edev.send = davinci_emac_send;
|
|
priv->edev.recv = davinci_emac_recv;
|
|
priv->edev.get_ethaddr = davinci_emac_get_ethaddr;
|
|
priv->edev.set_ethaddr = davinci_emac_set_ethaddr;
|
|
priv->edev.parent = dev;
|
|
|
|
davinci_eth_mdio_enable(priv);
|
|
|
|
start = get_time_ns();
|
|
while (1) {
|
|
phy_mask = readl(priv->adap_mdio + EMAC_MDIO_ALIVE);
|
|
if (phy_mask) {
|
|
dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
|
|
phy_mask = ~phy_mask;
|
|
break;
|
|
}
|
|
if (is_timeout(start, 256 * MSECOND)) {
|
|
dev_err(dev, "no live phy, scanning all\n");
|
|
phy_mask = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (pdata->interface_rmii)
|
|
priv->interface = PHY_INTERFACE_MODE_RMII;
|
|
else
|
|
priv->interface = PHY_INTERFACE_MODE_MII;
|
|
priv->phy_addr = pdata->phy_addr;
|
|
priv->phy_flags = pdata->force_link ? PHYLIB_FORCE_LINK : 0;
|
|
|
|
priv->miibus.read = davinci_miibus_read;
|
|
priv->miibus.write = davinci_miibus_write;
|
|
priv->miibus.priv = priv;
|
|
priv->miibus.parent = dev;
|
|
priv->miibus.phy_mask = phy_mask;
|
|
|
|
mdiobus_register(&priv->miibus);
|
|
|
|
eth_register(&priv->edev);
|
|
|
|
dev_dbg(dev, "- emac_probe\n");
|
|
return 0;
|
|
}
|
|
|
|
static void davinci_emac_remove(struct device_d *dev)
|
|
{
|
|
struct davinci_emac_priv *priv = dev->priv;
|
|
|
|
davinci_emac_halt(&priv->edev);
|
|
}
|
|
|
|
static struct driver_d davinci_emac_driver = {
|
|
.name = "davinci_emac",
|
|
.probe = davinci_emac_probe,
|
|
.remove = davinci_emac_remove,
|
|
};
|
|
device_platform_driver(davinci_emac_driver);
|