99 lines
2.0 KiB
ArmAsm
99 lines
2.0 KiB
ArmAsm
#include <config.h>
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#include <asm/arch/imx-regs.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/*
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* AHB-Lite IP Interface
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*/
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writel(0x20040304, AIPI1_PSR0)
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writel(0xDFFBFCFB, AIPI1_PSR1)
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writel(0x00000000, AIPI2_PSR0)
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writel(0xFFFFFFFF, AIPI2_PSR1)
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ldr r0, =CSCR
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ldr r1, [r0]
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bic r1, r1, #0x3
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str r1, [r0]
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writel(0x00041c02, MPCTL0)
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writel(0x04082008, SPCTL0)
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writel(0x33f00304, CSCR)
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writel(0x33f00300 | CSCR_FPM_EN | CSCR_MPEN | CSCR_SPEN | CSCR_MCU_SEL |
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CSCR_SP_SEL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART |
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0 ,
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CSCR)
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/* add some delay here */
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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writel(0x33f00300 | CSCR_FPM_EN | CSCR_MPEN | CSCR_SPEN | CSCR_MCU_SEL |
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CSCR_SP_SEL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART |
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CSCR_ARM_SRC_MPLL,
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CSCR)
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writel(0x00070f08, GPCR)
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writel(0x130410c3, PCDR0)
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writel(0x09030913, PCDR1)
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/* skip sdram setup for debugging */
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mov pc,r10
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0xa0000000
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bls 1f
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cmp pc, #0xc0000000
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bhi 1f
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mov pc,r10
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1:
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/*
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* DDR on CSD0
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*/
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writel(0x00000008, 0xD8001010)
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writel(0x55555555, 0x10027828)
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writel(0x55555555, 0x10027830)
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writel(0x55555555, 0x10027834)
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writel(0x00005005, 0x10027838)
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writel(0x15555555, 0x1002783C)
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2200000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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mov pc,r10
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