114 lines
5.0 KiB
C
114 lines
5.0 KiB
C
/* GENERATED FILE - DO NOT EDIT */
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/*
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Altera Corporation nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PRELOADER_PLL_CONFIG_H_
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#define _PRELOADER_PLL_CONFIG_H_
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#define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
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#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
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#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
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#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)
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#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
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#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
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#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
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#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
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#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
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#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
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#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)
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#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
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#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
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#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
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#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
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#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
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#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
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#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
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#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
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#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
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#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
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#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
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#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
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#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
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#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
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#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
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#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
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#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
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#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
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#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
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#define CONFIG_HPS_CLK_NAND_HZ (50000000)
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#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
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#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
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#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
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#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
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#define CONFIG_HPS_CLK_CAN1_HZ (12500000)
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#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
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#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
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#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
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#define CONFIG_HPS_ALTERAGRP_MPUCLK (1)
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#define CONFIG_HPS_ALTERAGRP_MAINCLK (3)
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#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
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#endif /* _PRELOADER_PLL_CONFIG_H_ */
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