102 lines
3.4 KiB
Plaintext
102 lines
3.4 KiB
Plaintext
/* MDMISC mirroring interleaved (row/bank/col) */
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wm 32 MX6_MMDC_P0_MDMISC 0x00000742
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check 32 while_all_bits_clear MX6_MMDC_P0_MDMISC 0x00000002
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wm 32 MX6_MMDC_P0_MDSCR 0x00008000
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check 32 while_any_bit_clear MX6_MMDC_P0_MDSCR 0x00004000
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wm 32 MX6_MMDC_P0_MDCTL 0x831a0000
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check 32 while_any_bit_clear MX6_MMDC_P0_MDMISC 0x40000000
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wm 32 MX6_MMDC_P0_MDCFG0 0x3f435333
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wm 32 MX6_MMDC_P0_MDCFG1 0x926e8a63
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wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db
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wm 32 MX6_MMDC_P0_MDRWD 0x000026d2
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wm 32 MX6_MMDC_P0_MDOR 0x00431023
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wm 32 MX6_MMDC_P0_MDOTC 0x1b333030
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wm 32 MX6_MMDC_P0_MDPDC 0x0002006d
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wm 32 MX6_MMDC_P1_MDPDC 0x0002006d
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wm 32 MX6_MMDC_P0_MDASP 0x00000027
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wm 32 MX6_MMDC_P0_MDSCR 0x05208030
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wm 32 MX6_MMDC_P0_MDSCR 0x00048031
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wm 32 MX6_MMDC_P0_MDSCR 0x00408032
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wm 32 MX6_MMDC_P0_MDSCR 0x00008033
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wm 32 MX6_MMDC_P0_MDREF 0x0000c000
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wm 32 MX6_MMDC_P0_MDSCR 0x00008020
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wm 32 MX6_MMDC_P0_MPODTCTRL 0x00022222
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wm 32 MX6_MMDC_P1_MPODTCTRL 0x00022222
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wm 32 MX6_MMDC_P0_MPPDCMPR2 0x00000003
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wm 32 MX6_MMDC_P0_MAPSR 0x00001007
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wm 32 MX6_MMDC_P0_MDSCR 0x04008010
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wm 32 MX6_MMDC_P0_MDSCR 0x04008040
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wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1390001
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check 32 while_all_bits_clear MX6_MMDC_P0_MPZQHWCTRL 0x00010000
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wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xA1380000
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wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x001e001e
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wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x001e001e
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wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001e001e
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wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x001e001e
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wm 32 MX6_MMDC_P0_MDSCR 0x00048033
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wm 32 MX6_IOM_DRAM_SDQS0 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS1 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS2 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS3 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS4 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS5 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS6 0x00007030
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wm 32 MX6_IOM_DRAM_SDQS7 0x00007030
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wm 32 MX6_MMDC_P0_MDSCR 0x00008020
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wm 32 MX6_MMDC_P0_MDSCR 0x04008050
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wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404040
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wm 32 MX6_MMDC_P0_MPWRDLCTL 0x40404040
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wm 32 MX6_MMDC_P1_MPRDDLCTL 0x40404040
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wm 32 MX6_MMDC_P1_MPWRDLCTL 0x40404040
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wm 32 MX6_MMDC_P0_MPMUR0 0x00000800
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wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
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check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
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wm 32 MX6_MMDC_P0_MPDGCTRL0 0x80000000
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check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x80000000
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wm 32 MX6_MMDC_P0_MPDGCTRL0 0x50800000
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check 32 while_all_bits_clear MX6_MMDC_P0_MPDGCTRL0 0x10001000
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wm 32 MX6_IOM_DRAM_SDQS0 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS1 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS2 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS3 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS4 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS5 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS6 0x00000030
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wm 32 MX6_IOM_DRAM_SDQS7 0x00000030
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wm 32 MX6_MMDC_P0_MDSCR 0x04008050
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wm 32 MX6_MMDC_P0_MPRDDLHWCTL 0x00000030
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wm 32 MX6_MMDC_P1_MPRDDLHWCTL 0x00000030
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check 32 while_all_bits_clear MX6_MMDC_P0_MPRDDLHWCTL 0x0000001f
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check 32 while_all_bits_clear MX6_MMDC_P1_MPRDDLHWCTL 0x0000001f
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wm 32 MX6_MMDC_P0_MDSCR 0x04008050
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wm 32 MX6_MMDC_P0_MPWRDLHWCTL 0x00000030
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check 32 while_all_bits_clear MX6_MMDC_P0_MPWRDLHWCTL 0x0000001f
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wm 32 MX6_MMDC_P0_MDSCR 0x04008050
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wm 32 MX6_MMDC_P1_MPWRDLHWCTL 0x00000030
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check 32 while_all_bits_clear MX6_MMDC_P1_MPWRDLHWCTL 0x0000001f
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wm 32 MX6_MMDC_P0_MDSCR 0x00008033
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wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa138002b
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wm 32 MX6_MMDC_P0_MDREF 0x00001800
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wm 32 MX6_MMDC_P0_MAPSR 0x00001006
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wm 32 MX6_MMDC_P0_MDPDC 0x0002556d
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wm 32 MX6_MMDC_P1_MDPDC 0x0002556d
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wm 32 MX6_MMDC_P0_MDSCR 0x00000000
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check 32 while_all_bits_clear MX6_MMDC_P0_MDSCR 0x00004000
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