460 lines
22 KiB
C
460 lines
22 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/omap4-silicon.h>
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#include <mach/omap4-mux.h>
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#include <mach/omap4-clock.h>
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#include "mux.h"
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static const struct pad_conf_entry core_padconf_array[] = {
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/* sdmmc2_dat0 */ /* internal FLASH */
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{ GPMC_AD0 , IEN | PTU | M1 },
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/* sdmmc2_dat1 */ /* internal FLASH */
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{ GPMC_AD1 , IEN | PTU | M1 },
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/* sdmmc2_dat2 */ /* internal FLASH */
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{ GPMC_AD2 , IEN | PTU | M1 },
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/* sdmmc2_dat3 */ /* internal FLASH */
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{ GPMC_AD3 , IEN | PTU | M1 },
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/* sdmmc2_dat4 */ /* internal FLASH */
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{ GPMC_AD4 , IEN | PTU | M1 },
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/* sdmmc2_dat5 */ /* internal FLASH */
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{ GPMC_AD5 , IEN | PTU | M1 },
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/* sdmmc2_dat6 */ /* internal FLASH */
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{ GPMC_AD6 , IEN | PTU | M1 },
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/* sdmmc2_dat7 */ /* internal FLASH */
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{ GPMC_AD7 , IEN | PTU | M1 },
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/* gpio_32 */
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{ GPMC_AD8 , IEN | PTD | M3 },
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/* gpmc_ad9 */
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{ GPMC_AD9 , IEN | PTU | M0 },
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/* gpio_34 */ /* 1v8_pwron */
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{ GPMC_AD10 , IEN | PTU | M3 },
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/* gpio_35 */ /* vcc_pwron */
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{ GPMC_AD11 , IEN | PTU | M3 },
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/* gpio_36 */ /* 5v_pwron */
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{ GPMC_AD12 , IEN | M3 },
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/* gpio_37 */ /* hdmi_pwr */
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{ GPMC_AD13 , IEN | M3 },
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/* gpio_38 */ /* lcd_pwon */
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{ GPMC_AD14 , IEN | M3 },
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/* gpio_39 */ /* lvds_en */
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{ GPMC_AD15 , IEN | M3 },
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/* gpio_40 */ /* 3g_enable */
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{ GPMC_A16 , IEN | M3 },
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/* gpio_41 */ /* gps_enable */
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{ GPMC_A17 , IEN | M3 },
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/* gpio_42 */ /* ehci_enable */
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{ GPMC_A18 , IEN | M3 },
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/* gpio_43 */ /* volume up */
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{ GPMC_A19 , IEN | M3 },
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/* gpio_44 */ /* volume down */
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{ GPMC_A20 , IEN | M3 },
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/* gpio_45 */ /* accel_int1 */
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{ GPMC_A21 , IEN | PTU | M3 },
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/* kpd_col6 */
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{ GPMC_A22 , IEN | PTD | M1 },
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/* kpd_col7 */
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{ GPMC_A23 , IEN | PTD | M1 },
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/* gpio_48 */ /* vbus_detect */
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{ GPMC_A24 , IEN | M3 },
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/* gpio_49 */ /* id */
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{ GPMC_A25 , IEN | PTU | M3 },
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/* gpmc_ncs0 */
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{ GPMC_NCS0 , IEN | PTU | M0 },
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/* gpio_51 */ /* compass_data_ready */
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{ GPMC_NCS1 , IEN | M3 },
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/* safe_mode */
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{ GPMC_NCS2 , IEN | PTU | M7 },
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/* gpio_53 */ /* lcd_rst */
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{ GPMC_NCS3 , IEN | M3 },
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/* gpmc_nwp */
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{ GPMC_NWP , IEN | PTD | M0 },
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/* gpmc_clk */
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{ GPMC_CLK , IEN | PTD | M0 },
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/* gpmc_nadv_ale */
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{ GPMC_NADV_ALE , IEN | PTD | M0 },
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/* sdmmc2_clk */ /* internal FLASH */
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{ GPMC_NOE , IEN | PTU | M1 },
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/* sdmmc2_cmd */ /* internal FLASH */
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{ GPMC_NWE , IEN | PTU | M1 },
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/* gpmc_nbe0_cle */
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{ GPMC_NBE0_CLE , IEN | PTD | M0 },
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/* safe_mode */
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{ GPMC_NBE1 , IEN | PTD | M7 },
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/* gpmc_wait0 */
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{ GPMC_WAIT0 , IEN | PTU | M0 },
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/* gpio_62 */ /* camera_reset */
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{ GPMC_WAIT1 , IEN | M3 },
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/* safe_mode */
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{ GPMC_WAIT2 , IEN | PTD | M7 },
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/* gpio_101 */ /* lcd_stdby */
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{ GPMC_NCS4 , M3 },
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/* gpio_102 */ /* wifi_irq */
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{ GPMC_NCS5 , IEN | M3 },
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/* gpio_103 */ /* wifi_power */
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{ GPMC_NCS6 , M3 },
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/* gpio_104 */ /* bt_power */
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{ GPMC_NCS7 , IEN | M3 },
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/* gpio_63 */ /* hdmi_hpd ?? */
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{ GPIO63 , IEN | PTD | M3 },
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/* */
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{ GPIO64 , IEN | M0 },
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/* */
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{ GPIO65 , IEN | M0 },
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/* */
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{ GPIO66 , IEN | M0 },
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/* csi21_dx0 */
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{ CSI21_DX0 , IEN | M0 },
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/* csi21_dy0 */
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{ CSI21_DY0 , IEN | M0 },
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/* csi21_dx1 */
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{ CSI21_DX1 , IEN | M0 },
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/* csi21_dy1 */
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{ CSI21_DY1 , IEN | M0 },
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/* safe_mode */
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{ CSI21_DX2 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI21_DY2 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI21_DX3 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI21_DY3 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI21_DX4 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI21_DY4 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI22_DX0 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI22_DY0 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI22_DX1 , IEN | PTD | M7 },
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/* safe_mode */
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{ CSI22_DY1 , IEN | PTD | M7 },
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/* cam_shutter */
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{ CAM_SHUTTER , PTD | M0 },
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/* cam_strobe */
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{ CAM_STROBE , PTD | M0 },
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/* gpio_83 */
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{ CAM_GLOBALRESET , PTD | M3 },
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/* usbb1_ulpiphy_clk */
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{ USBB1_ULPITLL_CLK , IEN | PTD | M4 },
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/* usbb1_ulpiphy_stp */
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{ USBB1_ULPITLL_STP , M4 },
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/* usbb1_ulpiphy_dir */
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{ USBB1_ULPITLL_DIR , IEN | PTD | M4 },
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/* usbb1_ulpiphy_nxt */
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{ USBB1_ULPITLL_NXT , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat0 */
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{ USBB1_ULPITLL_DAT0 , WAKEUP_EN | IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat1 */
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{ USBB1_ULPITLL_DAT1 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat2 */
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{ USBB1_ULPITLL_DAT2 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat3 */
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{ USBB1_ULPITLL_DAT3 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat4 */
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{ USBB1_ULPITLL_DAT4 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat5 */
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{ USBB1_ULPITLL_DAT5 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat6 */
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{ USBB1_ULPITLL_DAT6 , IEN | PTD | M4 },
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/* usbb1_ulpiphy_dat7 */
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{ USBB1_ULPITLL_DAT7 , IEN | PTD | M4 },
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/* usbb1_hsic_data */
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{ USBB1_HSIC_DATA , M0 },
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/* usbb1_hsic_strobe */
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{ USBB1_HSIC_STROBE , M0 },
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/* usbc1_icusb_dp */
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{ USBC1_ICUSB_DP , M0 },
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/* usbc1_icusb_dm */
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{ USBC1_ICUSB_DM , M0 },
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/* sdmmc1_clk */ /* SD card */
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{ SDMMC1_CLK , PTU | M0 },
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/* sdmmc1_cmd */ /* SD card */
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{ SDMMC1_CMD , IEN | PTU | M0 },
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/* sdmmc1_dat0 */ /* SD card */
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{ SDMMC1_DAT0 , IEN | PTU | M0 },
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/* sdmmc1_dat1 */ /* SD card */
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{ SDMMC1_DAT1 , IEN | PTU | M0 },
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/* sdmmc1_dat2 */ /* SD card */
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{ SDMMC1_DAT2 , IEN | PTU | M0 },
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/* sdmmc1_dat3 */ /* SD card */
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{ SDMMC1_DAT3 , IEN | PTU | M0 },
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/* sdmmc1_dat4 */ /* SD card */
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{ SDMMC1_DAT4 , IEN | PTU | M0 },
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/* sdmmc1_dat5 */ /* SD card */
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{ SDMMC1_DAT5 , IEN | PTU | M0 },
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/* sdmmc1_dat6 */ /* SD card */
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{ SDMMC1_DAT6 , IEN | PTU | M0 },
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/* sdmmc1_dat7 */ /* SD card */
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{ SDMMC1_DAT7 , IEN | PTU | M0 },
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/* gpio_110 */ /* tsp_pwr_gpio */
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{ ABE_MCBSP2_CLKX , M3 },
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/* gpio_111 */ /* vbus_musb_pwron */
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{ ABE_MCBSP2_DR , IEN | M3 },
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/* gpio_112 */ /* tsp_irq_gpio */
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{ ABE_MCBSP2_DX , WAKEUP_EN | IEN | PTU | M3 },
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/* gpio_113 */ /* vbus_flag */
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{ ABE_MCBSP2_FSX , IEN | PTU | M3 },
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/* safe_mode */
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{ ABE_MCBSP1_CLKX , IEN | PTD | M7 },
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/* safe_mode */
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{ ABE_MCBSP1_DR , IEN | PTD | M7 },
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/* abe_mcbsp1_dx */
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{ ABE_MCBSP1_DX , M0 },
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/* abe_mcbsp1_fsx */
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{ ABE_MCBSP1_FSX , IEN | M0 },
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/* abe_pdm_ul_data */
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{ ABE_PDM_UL_DATA , IEN | M0 },
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/* abe_pdm_dl_data */
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{ ABE_PDM_DL_DATA , M0 },
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/* abe_pdm_frame */
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{ ABE_PDM_FRAME , IEN | M0 },
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/* abe_pdm_lb_clk */
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{ ABE_PDM_LB_CLK , IEN | M0 },
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/* abe_clks */
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{ ABE_CLKS , IEN | M0 },
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/* safe_mode */
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{ ABE_DMIC_CLK1 , IEN | PTD | M7 },
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/* safe_mode */
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{ ABE_DMIC_DIN1 , IEN | PTD | M7 },
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/* safe_mode */
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{ ABE_DMIC_DIN2 , IEN | PTD | M7 },
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/* safe_mode */ /* bkl_en on gpio_122 ?? */
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{ ABE_DMIC_DIN3 , IEN | PTD | M7 },
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/* uart2_cts */
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{ UART2_CTS , WAKEUP_EN | OFF_PU | OFF_IN | M0 },
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/* safe_mode */
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{ UART2_RTS , OFF_PU | OFF_IN | M7 },
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/* uart2_rx */
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{ UART2_RX , IEN | PTU | M0 },
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/* uart2_tx */
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{ UART2_TX , M0 },
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/* gpio_127 */ /* audio_power_on */
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{ HDQ_SIO , M3 },
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/* i2c1_scl */
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{ I2C1_SCL , IEN | M0 },
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/* i2c1_sda */
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{ I2C1_SDA , IEN | M0 },
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/* i2c2_scl */
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{ I2C2_SCL , IEN | M0 },
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/* i2c2_sda */
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{ I2C2_SDA , IEN | M0 },
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/* i2c3_scl */
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{ I2C3_SCL , IEN | M0 },
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/* i2c3_sda */
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{ I2C3_SDA , IEN | M0 },
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/* i2c4_scl */
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{ I2C4_SCL , IEN | M0 },
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/* i2c4_sda */
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{ I2C4_SDA , IEN | M0 },
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/* mcspi1_clk */
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{ MCSPI1_CLK , IEN | M0 },
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/* mcspi1_somi */
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{ MCSPI1_SOMI , IEN | M0 },
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/* mcspi1_simo */
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{ MCSPI1_SIMO , IEN | M0 },
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/* mcspi1_cs0 */
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{ MCSPI1_CS0 , IEN | PTD | M0 },
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/* uart1_rx */
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{ MCSPI1_CS1 , WAKEUP_EN | IEN | M1 },
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/* gpio_139 */
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{ MCSPI1_CS2 , M3 },
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/* safe_mode */
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{ MCSPI1_CS3 , IEN | PTU | M7 },
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/* uart1_tx */
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{ UART3_CTS_RCTX , M1 },
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/* uart3_rts_sd */
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{ UART3_RTS_SD , M0 },
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/* safe_mode */
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{ UART3_RX_IRRX , IEN | PTU | M7 },
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/* safe_mode */
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{ UART3_TX_IRTX , IEN | PTD | M7 },
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/* sdmmc5_clk */
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{ SDMMC5_CLK , PTU | M0 },
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/* sdmmc5_cmd */
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{ SDMMC5_CMD , IEN | PTU | M0 },
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/* sdmmc5_dat0 */
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{ SDMMC5_DAT0 , IEN | PTU | M0 },
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/* sdmmc5_dat1 */
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{ SDMMC5_DAT1 , IEN | PTU | M0 },
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/* sdmmc5_dat2 */
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{ SDMMC5_DAT2 , IEN | PTU | M0 },
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/* sdmmc5_dat3 */
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{ SDMMC5_DAT3 , IEN | PTU | M0 },
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/* sdmmc4_clk */
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{ MCSPI4_CLK , IEN | PTU | M1 },
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/* sdmmc4_cmd */
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{ MCSPI4_SIMO , IEN | PTU | M1 },
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/* sdmmc4_dat0 */
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{ MCSPI4_SOMI , IEN | PTU | M1 },
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/* sdmmc4_dat3 */
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{ MCSPI4_CS0 , IEN | PTU | M1 },
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/* sdmmc4_dat2 */
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{ UART4_RX , IEN | PTU | M1 },
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/* sdmmc4_dat1 */
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{ UART4_TX , IEN | PTU | M1 },
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/* gpio_157 */
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{ USBB2_ULPITLL_CLK , M3 },
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/* dispc2_data23 */
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{ USBB2_ULPITLL_STP , M5 },
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/* dispc2_data22 */
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{ USBB2_ULPITLL_DIR , M5 },
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/* dispc2_data21 */
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{ USBB2_ULPITLL_NXT , M5 },
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/* dispc2_data20 */
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{ USBB2_ULPITLL_DAT0 , M5 },
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/* dispc2_data19 */
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{ USBB2_ULPITLL_DAT1 , M5 },
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/* dispc2_data18 */
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{ USBB2_ULPITLL_DAT2 , M5 },
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/* dispc2_data15 */
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{ USBB2_ULPITLL_DAT3 , M5 },
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/* dispc2_data14 */
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{ USBB2_ULPITLL_DAT4 , M5 },
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/* dispc2_data13 */
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{ USBB2_ULPITLL_DAT5 , M5 },
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/* dispc2_data12 */
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{ USBB2_ULPITLL_DAT6 , M5 },
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/* dispc2_data11 */
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{ USBB2_ULPITLL_DAT7 , M5 },
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/* gpio_169 */
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{ USBB2_HSIC_DATA , M3 },
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/* gpio_170 */
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{ USBB2_HSIC_STROBE , M3 },
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/* kpd_col0 */
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{ KPD_COL3 , IEN | PTD | M1 },
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/* kpd_col1 */
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{ KPD_COL4 , IEN | PTD | M1 },
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/* kpd_col2 */
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{ KPD_COL5 , IEN | PTD | M1 },
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/* gpio_174 */ /* accel_int2 */
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{ KPD_COL0 , IEN | PTU | M3 },
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/* gpio_0 */ /* tsp_shtdwn_gpio */
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{ KPD_COL1 , IEN | PTD | M3 },
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/* gpio_1 */
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{ KPD_COL2 , IEN | PTD | M3 },
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/* kpd_row0 */
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{ KPD_ROW3 , IEN | PTD | M1 },
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/* kpd_row1 */
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{ KPD_ROW4 , IEN | PTD | M1 },
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/* kpd_row2 */
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{ KPD_ROW5 , IEN | PTD | M1 },
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/* kpd_row3 */
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{ KPD_ROW0 , IEN | PTD | M1 },
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/* kpd_row4 */
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{ KPD_ROW1 , IEN | PTD | M1 },
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/* kpd_row5 */
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{ KPD_ROW2 , IEN | PTD | M1 },
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/* usba0_otg_ce */
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{ USBA0_OTG_CE , PTU | M0 },
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/* usba0_otg_dp */
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{ USBA0_OTG_DP , M0 },
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/* usba0_otg_dm */
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{ USBA0_OTG_DM , M0 },
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/* safe_mode */
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{ FREF_CLK1_OUT , IEN | PTD | M7 },
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/* fref_clk2_out */
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{ FREF_CLK2_OUT , M0 },
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/* sys_nirq1 */
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{ SYS_NIRQ1 , WAKEUP_EN | IEN | PTU | M0 },
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/* sys_nirq2 */ /* audio_irq */
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{ SYS_NIRQ2 , IEN | PTU | M0 },
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/* sys_boot0 */
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{ SYS_BOOT0 , IEN | PTD | M0 },
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/* sys_boot1 */
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{ SYS_BOOT1 , IEN | PTD | M0 },
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/* sys_boot2 */
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{ SYS_BOOT2 , IEN | PTD | M0 },
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/* sys_boot3 */
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{ SYS_BOOT3 , IEN | PTD | M0 },
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/* sys_boot4 */
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{ SYS_BOOT4 , IEN | PTD | M0 },
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/* sys_boot5 */
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{ SYS_BOOT5 , IEN | PTD | M0 },
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/* dpm_emu0 */
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{ DPM_EMU0 , IEN | PTU | M0 },
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/* gpio_12 */ /* lcd_avdd_en */
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{ DPM_EMU1 , IEN | M3 },
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/* safe_mode */
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{ DPM_EMU2 , IEN | PTD | M7 },
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/* dispc2_data10 */
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{ DPM_EMU3 , M5 },
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/* dispc2_data9 */
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{ DPM_EMU4 , M5 },
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/* dispc2_data16 */
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{ DPM_EMU5 , M5 },
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/* dispc2_data17 */
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{ DPM_EMU6 , M5 },
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/* dispc2_hsync */
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|
{ DPM_EMU7 , M5 },
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|
/* dispc2_pclk */
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|
{ DPM_EMU8 , M5 },
|
|
/* dispc2_vsync */
|
|
{ DPM_EMU9 , M5 },
|
|
/* dispc2_de */
|
|
{ DPM_EMU10 , M5 },
|
|
/* dispc2_data8 */
|
|
{ DPM_EMU11 , M5 },
|
|
/* dispc2_data7 */
|
|
{ DPM_EMU12 , M5 },
|
|
/* dispc2_data6 */
|
|
{ DPM_EMU13 , M5 },
|
|
/* dispc2_data5 */
|
|
{ DPM_EMU14 , M5 },
|
|
/* dispc2_data4 */
|
|
{ DPM_EMU15 , M5 },
|
|
/* dispc2_data3 */
|
|
{ DPM_EMU16 , M5 },
|
|
/* dispc2_data2 */
|
|
{ DPM_EMU17 , M5 },
|
|
/* dispc2_data1 */
|
|
{ DPM_EMU18 , M5 },
|
|
/* dispc2_data0 */
|
|
{ DPM_EMU19 , M5 },
|
|
/* safe_mode */
|
|
{ CSI22_DX2 , IEN | PTD | M7 },
|
|
/* safe_mode */
|
|
{ CSI22_DY2 , IEN | PTD | M7 },
|
|
};
|
|
|
|
static const struct pad_conf_entry wkup_padconf_array[] = {
|
|
/* sr_scl */
|
|
{ SR_SCL , IEN },
|
|
/* sr_sda */
|
|
{ SR_SDA , IEN },
|
|
/* fref_clk0_out */
|
|
{ FREF_CLK0_OUT , M0 },
|
|
/* gpio_wk30 */
|
|
{ FREF_CLK3_REQ , M3 },
|
|
/* gpio_wk7 */ /* tps62361_vsel0 */
|
|
{ FREF_CLK4_REQ , IEN | PTU | M3 },
|
|
};
|
|
|
|
void set_muxconf_regs(void){
|
|
omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE,
|
|
core_padconf_array, ARRAY_SIZE(core_padconf_array));
|
|
omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP,
|
|
wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array));
|
|
|
|
/* gpio_wk7 is used for controlling TPS on 4460 */
|
|
if (omap4_revision() >= OMAP4460_ES1_0) {
|
|
writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ);
|
|
/* Enable GPIO-1 clocks before TPS initialization */
|
|
omap4_enable_gpio1_wup_clocks();
|
|
}
|
|
}
|