267 lines
8.9 KiB
C
267 lines
8.9 KiB
C
#include <init.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <asm/armlinux.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <linux/bitops.h>
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#include <mach/am33xx-generic.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/wdt.h>
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#include <debug_ll.h>
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/* AM335X EMIF Register values */
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_LOCK_EN (0x1 << 4)
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#define VTP_CTRL_START_EN (0x1)
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#define DDR2_RATIO 0x80 /* for mDDR */ //
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#define CMD_FORCE 0x00 /* common #def */
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#define CMD_DELAY 0x00
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#define EMIF_READ_LATENCY 0x05 // (CL + 2 - 1)
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#define EMIF_TIM1 0x04447289 //
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#define EMIF_TIM2 0x10160580 //
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#define EMIF_TIM3 0x000000E7 // check tREFI
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#define EMIF_SDCFG 0x0 \
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| (1 << 29) /* reg_sdram_type = 1 (LPDDR1) */ \
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| (0 << 27) /* reg_ibank_pos = 0 */ \
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| (0 << 24) /* reg_ddr_term = 0? */ \
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| (0 << 23) /* reg_ddr2_ddqs = 0 (single ended DQS for LPDDR) */ \
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| (0 << 21) /* reg_dyn_odt = 0 (only used for DDR3) */ \
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| (0 << 20) /* reg_ddr_disable_dll = 0 */ \
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| (1 << 18) /* reg_sdram_drive = 1? (1/2 for LPDDR) */ \
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| (0 << 16) /* reg_cwl = 0 (only for DDR3) */ \
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| (1 << 14) /* reg_narrow_mode = 1 (AM335x is always 16 bit) */ \
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| (3 << 10) /* reg_cl = 3 */ \
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| (5 << 7) /* reg_rowsize = 5 (unused?, 14 row bits) */ \
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| (2 << 4) /* reg_ibank = 2 (4 banks) */ \
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| (0 << 3) /* reg_ebank = 0 */ \
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| (3 << 0) /* reg_pagesize = 3? (11 column bits = 2048 words) */
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#define EMIF_SDREF 0x00000618 //
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#define DDR2_DLL_LOCK_DIFF 0x0
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#define DDR2_RD_DQS 0x40 //
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#define DDR2_WR_DQS 0x2 //
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_FIFO_WE 0x110 //
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#define DDR2_PHY_WR_DATA 0x40 //
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#define DDR2_INVERT_CLKOUT 0x0 //
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#define PHY_RANK0_DELAY 0x1 //
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#define PHY_DLL_LOCK_DIFF 0x0
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#define DDR_IOCTRL_VALUE 0x18B //
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static void board_data_macro_config(int dataMacroNum)
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{
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u32 BaseAddrOffset = 0x00;
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if (dataMacroNum == 1)
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BaseAddrOffset = 0xA4;
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__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
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|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
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(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_RD_DQS>>2,
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(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
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|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
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(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_WR_DQS>>2,
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(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
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|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
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(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_WRLVL>>2,
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(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
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|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
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(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_GATELVL>>2,
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(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
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|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
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(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_FIFO_WE>>2,
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(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
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|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
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(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
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__raw_writel(DDR2_PHY_WR_DATA>>2,
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(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
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__raw_writel(PHY_DLL_LOCK_DIFF,
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(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
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}
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static void board_cmd_macro_config(void)
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{
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__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
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__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
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__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
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__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
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__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
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__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
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__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
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}
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static void board_config_vtp(void)
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{
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
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AM33XX_VTP0_CTRL_REG);
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
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AM33XX_VTP0_CTRL_REG);
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__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
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AM33XX_VTP0_CTRL_REG);
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/* Poll for READY */
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while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
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}
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static void board_config_emif_ddr(void)
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{
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u32 i;
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/*Program EMIF0 CFG Registers*/
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
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__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
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__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
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__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
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__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
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__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
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__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
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__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
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__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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for (i = 0; i < 5000; i++) {
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}
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__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
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__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
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__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
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}
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static void board_config_ddr(void)
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{
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am33xx_enable_ddr_clocks();
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board_config_vtp();
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board_cmd_macro_config();
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board_data_macro_config(0);
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board_data_macro_config(1);
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__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
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__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
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__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
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__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) | BIT(28), AM33XX_DDR_IO_CTRL);
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__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | BIT(0), AM33XX_DDR_CKE_CTRL);
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board_config_emif_ddr();
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}
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static const struct module_pin_mux board_can_pin_mux[] = {
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{OFFSET(mii1_txd3), (MODE(1) | PULLUP_EN)}, /* dcan0_tx_mux0 */
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{OFFSET(mii1_txd2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* dcan0_rx_mux0 */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUP_EN)}, /* gpio3[18] / DCAN0_LBK */
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{-1},
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};
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extern char __dtb_z_am335x_afi_gf_start[];
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static noinline int gf_sram_init(void)
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{
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void *fdt;
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fdt = __dtb_z_am335x_afi_gf_start;
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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/* Setup the PLLs and the clocks for the peripherals */
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am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200);
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board_config_ddr();
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/*
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* FIXME configure CAN pinmux early to avoid driving the bus
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* with the low by default pins.
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*/
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configure_module_pin_mux(board_can_pin_mux);
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am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE);
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am33xx_enable_uart2_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE);
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putc_ll('>');
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barebox_arm_entry(0x80000000, SZ_256M, fdt);
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}
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ENTRY_FUNCTION(start_am33xx_afi_gf_sram, bootinfo, r1, r2)
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{
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am33xx_save_bootinfo((void *)bootinfo);
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/*
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* Setup C environment, the board init code uses global variables.
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* Stackpointer has already been initialized by the ROM code.
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*/
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relocate_to_current_adr();
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setup_c();
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gf_sram_init();
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}
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ENTRY_FUNCTION(start_am33xx_afi_gf_sdram, r0, r1, r2)
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{
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void *fdt;
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fdt = __dtb_z_am335x_afi_gf_start - get_runtime_offset();
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putc_ll('>');
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barebox_arm_entry(0x80000000, SZ_256M, fdt);
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}
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