157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
/*
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* Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* Based on the Linux ath79 clock code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/ath79.h>
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#include <dt-bindings/clock/ath79-clk.h>
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static struct clk *clks[ATH79_CLK_END];
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static struct clk_onecell_data clk_data;
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struct clk_ar933x {
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struct clk clk;
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void __iomem *base;
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u32 div_shift;
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u32 div_mask;
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const char *parent;
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};
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static unsigned long clk_ar933x_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_ar933x *f = container_of(clk, struct clk_ar933x, clk);
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unsigned long rate;
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unsigned long freq;
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u32 clock_ctrl;
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u32 cpu_config;
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u32 t;
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clock_ctrl = __raw_readl(f->base + AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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rate = parent_rate;
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} else {
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cpu_config = __raw_readl(f->base + AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = parent_rate / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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freq *= t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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freq >>= t;
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t = ((clock_ctrl >> f->div_shift) & f->div_mask) + 1;
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rate = freq / t;
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}
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return rate;
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}
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struct clk_ops clk_ar933x_ops = {
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.recalc_rate = clk_ar933x_recalc_rate,
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};
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static struct clk *clk_ar933x(const char *name, const char *parent,
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void __iomem *base, u32 div_shift, u32 div_mask)
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{
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struct clk_ar933x *f = xzalloc(sizeof(*f));
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f->parent = parent;
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f->base = base;
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f->div_shift = div_shift;
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f->div_mask = div_mask;
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f->clk.ops = &clk_ar933x_ops;
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f->clk.name = name;
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f->clk.parent_names = &f->parent;
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f->clk.num_parents = 1;
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clk_register(&f->clk);
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return &f->clk;
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}
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static void ar933x_pll_init(void __iomem *base)
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{
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clks[ATH79_CLK_CPU] = clk_ar933x("cpu", "ref", base,
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK);
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clks[ATH79_CLK_DDR] = clk_ar933x("ddr", "ref", base,
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK);
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clks[ATH79_CLK_AHB] = clk_ar933x("ahb", "ref", base,
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK);
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}
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static int ar933x_clk_probe(struct device_d *dev)
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{
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struct resource *iores;
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void __iomem *base;
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iores = dev_request_mem_resource(dev, 0);
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if (IS_ERR(iores))
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return PTR_ERR(iores);
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base = IOMEM(iores->start);
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ar933x_pll_init(base);
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
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&clk_data);
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return 0;
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}
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static __maybe_unused struct of_device_id ar933x_clk_dt_ids[] = {
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{
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.compatible = "qca,ar9330-pll",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d ar933x_clk_driver = {
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.probe = ar933x_clk_probe,
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.name = "ar933x_clk",
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.of_compatible = DRV_OF_COMPAT(ar933x_clk_dt_ids),
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};
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static int ar933x_clk_init(void)
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{
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return platform_driver_register(&ar933x_clk_driver);
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}
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postcore_initcall(ar933x_clk_init);
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