489 lines
13 KiB
C
489 lines
13 KiB
C
#define pr_fmt(fmt) "pci: " fmt
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#include <common.h>
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#include <linux/sizes.h>
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#include <linux/pci.h>
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static struct pci_controller *hose_head, **hose_tail = &hose_head;
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LIST_HEAD(pci_root_buses);
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EXPORT_SYMBOL(pci_root_buses);
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static u8 bus_index;
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static resource_size_t last_mem;
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static resource_size_t last_mem_pref;
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static resource_size_t last_io;
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static struct pci_bus *pci_alloc_bus(void)
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{
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struct pci_bus *b;
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b = xzalloc(sizeof(*b));
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INIT_LIST_HEAD(&b->node);
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INIT_LIST_HEAD(&b->children);
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INIT_LIST_HEAD(&b->devices);
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INIT_LIST_HEAD(&b->slots);
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INIT_LIST_HEAD(&b->resources);
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return b;
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}
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void register_pci_controller(struct pci_controller *hose)
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{
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struct pci_bus *bus;
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*hose_tail = hose;
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hose_tail = &hose->next;
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bus = pci_alloc_bus();
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hose->bus = bus;
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bus->parent = hose->parent;
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bus->host = hose;
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bus->ops = hose->pci_ops;
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bus->resource[PCI_BUS_RESOURCE_MEM] = hose->mem_resource;
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bus->resource[PCI_BUS_RESOURCE_MEM_PREF] = hose->mem_pref_resource;
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bus->resource[PCI_BUS_RESOURCE_IO] = hose->io_resource;
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bus->number = bus_index++;
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if (hose->set_busno)
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hose->set_busno(hose, bus->number);
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if (bus->resource[PCI_BUS_RESOURCE_MEM])
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last_mem = bus->resource[PCI_BUS_RESOURCE_MEM]->start;
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else
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last_mem = 0;
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if (bus->resource[PCI_BUS_RESOURCE_MEM_PREF])
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last_mem_pref = bus->resource[PCI_BUS_RESOURCE_MEM_PREF]->start;
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else
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last_mem_pref = 0;
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if (bus->resource[PCI_BUS_RESOURCE_IO])
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last_io = bus->resource[PCI_BUS_RESOURCE_IO]->start;
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else
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last_io = 0;
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pci_scan_bus(bus);
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list_add_tail(&bus->node, &pci_root_buses);
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return;
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}
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size,type,len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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return res; \
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}
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#define PCI_OP_WRITE(size,type,len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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static struct pci_dev *alloc_pci_dev(void)
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{
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struct pci_dev *dev;
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dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
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if (!dev)
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return NULL;
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INIT_LIST_HEAD(&dev->bus_list);
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return dev;
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}
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static u32 pci_size(u32 base, u32 maxbase, u32 mask)
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{
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u32 size = maxbase & mask;
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if (!size)
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return 0;
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size = (size & ~(size-1)) - 1;
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size + 1;
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}
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static void setup_device(struct pci_dev *dev, int max_bar)
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{
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int bar;
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u8 cmd;
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pci_read_config_byte(dev, PCI_COMMAND, &cmd);
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pci_write_config_byte(dev, PCI_COMMAND,
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cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
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for (bar = 0; bar < max_bar; bar++) {
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resource_size_t last_addr;
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u32 orig, mask, size;
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &orig);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, 0xfffffffe);
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pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, &mask);
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, orig);
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if (mask == 0 || mask == 0xffffffff) {
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pr_debug("pbar%d set bad mask\n", bar);
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continue;
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}
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if (mask & 0x01) { /* IO */
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size = pci_size(orig, mask, 0xfffffffe);
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if (!size) {
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pr_debug("pbar%d bad IO mask\n", bar);
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continue;
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}
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pr_debug("pbar%d: mask=%08x io %d bytes\n", bar, mask, size);
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if (last_io + size >
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dev->bus->resource[PCI_BUS_RESOURCE_IO]->end) {
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pr_debug("BAR does not fit within bus IO res\n");
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return;
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}
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_io);
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dev->resource[bar].flags = IORESOURCE_IO;
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last_addr = last_io;
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last_io += size;
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} else if ((mask & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
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last_mem_pref) /* prefetchable MEM */ {
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size = pci_size(orig, mask, 0xfffffff0);
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if (!size) {
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pr_debug("pbar%d bad P-MEM mask\n", bar);
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continue;
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}
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pr_debug("pbar%d: mask=%08x P memory %d bytes\n",
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bar, mask, size);
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if (last_mem_pref + size >
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dev->bus->resource[PCI_BUS_RESOURCE_MEM_PREF]->end) {
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pr_debug("BAR does not fit within bus p-mem res\n");
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return;
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}
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem_pref);
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dev->resource[bar].flags = IORESOURCE_MEM |
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IORESOURCE_PREFETCH;
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last_addr = last_mem_pref;
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last_mem_pref += size;
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} else { /* non-prefetch MEM */
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size = pci_size(orig, mask, 0xfffffff0);
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if (!size) {
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pr_debug("pbar%d bad NP-MEM mask\n", bar);
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continue;
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}
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pr_debug("pbar%d: mask=%08x NP memory %d bytes\n",
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bar, mask, size);
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if (last_mem + size >
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dev->bus->resource[PCI_BUS_RESOURCE_MEM]->end) {
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pr_debug("BAR does not fit within bus np-mem res\n");
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return;
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}
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar * 4, last_mem);
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dev->resource[bar].flags = IORESOURCE_MEM;
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last_addr = last_mem;
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last_mem += size;
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}
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dev->resource[bar].start = last_addr;
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dev->resource[bar].end = last_addr + size - 1;
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if ((mask & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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dev->resource[bar].flags |= IORESOURCE_MEM_64;
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pci_write_config_dword(dev,
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PCI_BASE_ADDRESS_1 + bar * 4, 0);
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bar++;
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}
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}
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pci_write_config_byte(dev, PCI_COMMAND, cmd);
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list_add_tail(&dev->bus_list, &dev->bus->devices);
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}
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static void prescan_setup_bridge(struct pci_dev *dev)
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{
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u16 cmdstat;
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pci_read_config_word(dev, PCI_COMMAND, &cmdstat);
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/* Configure bus number registers */
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pci_write_config_byte(dev, PCI_PRIMARY_BUS, dev->bus->number);
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pci_write_config_byte(dev, PCI_SECONDARY_BUS, dev->subordinate->number);
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff);
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if (last_mem) {
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_write_config_word(dev, PCI_MEMORY_BASE,
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(last_mem & 0xfff00000) >> 16);
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (last_mem_pref) {
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,
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(last_mem_pref & 0xfff00000) >> 16);
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cmdstat |= PCI_COMMAND_MEMORY;
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} else {
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/* We don't support prefetchable memory for now, so disable */
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pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x1000);
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
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}
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if (last_io) {
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pci_write_config_byte(dev, PCI_IO_BASE,
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(last_io & 0x0000f000) >> 8);
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pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
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(last_io & 0xffff0000) >> 16);
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cmdstat |= PCI_COMMAND_IO;
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}
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/* Enable memory and I/O accesses, enable bus master */
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pci_write_config_word(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
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}
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static void postscan_setup_bridge(struct pci_dev *dev)
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{
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/* limit subordinate to last used bus number */
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pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, bus_index - 1);
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if (last_mem) {
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last_mem = ALIGN(last_mem, SZ_1M);
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pci_write_config_word(dev, PCI_MEMORY_LIMIT,
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((last_mem - 1) & 0xfff00000) >> 16);
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}
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if (last_mem_pref) {
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last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
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pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
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((last_mem_pref - 1) & 0xfff00000) >> 16);
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}
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if (last_io) {
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last_io = ALIGN(last_io, SZ_4K);
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pci_write_config_byte(dev, PCI_IO_LIMIT,
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((last_io - 1) & 0x0000f000) >> 8);
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pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
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((last_io - 1) & 0xffff0000) >> 16);
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}
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}
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unsigned int pci_scan_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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struct pci_bus *child_bus;
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unsigned int devfn, l, max, class;
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unsigned char cmd, tmp, hdr_type, is_multi = 0;
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pr_debug("pci_scan_bus for bus %d\n", bus->number);
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pr_debug(" last_io = 0x%08x, last_mem = 0x%08x, last_mem_pref = 0x%08x\n",
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last_io, last_mem, last_mem_pref);
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max = bus->secondary;
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for (devfn = 0; devfn < 0xff; ++devfn) {
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if (PCI_FUNC(devfn) && !is_multi) {
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/* not a multi-function device */
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continue;
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}
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if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
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continue;
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if (!PCI_FUNC(devfn))
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is_multi = hdr_type & 0x80;
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l) ||
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/* some broken boards return 0 if a slot is empty: */
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l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
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continue;
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dev = alloc_pci_dev();
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if (!dev)
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return 0;
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dev->bus = bus;
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dev->devfn = devfn;
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dev->vendor = l & 0xffff;
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dev->device = (l >> 16) & 0xffff;
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dev->dev.parent = bus->parent;
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/* non-destructively determine if device can be a master: */
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pci_read_config_byte(dev, PCI_COMMAND, &cmd);
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pci_write_config_byte(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
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pci_read_config_byte(dev, PCI_COMMAND, &tmp);
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pci_write_config_byte(dev, PCI_COMMAND, cmd);
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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class >>= 8;
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dev->hdr_type = hdr_type;
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pr_debug("class = %08x, hdr_type = %08x\n", class, hdr_type);
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pr_debug("%02x:%02x [%04x:%04x]\n", bus->number, dev->devfn,
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dev->vendor, dev->device);
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switch (hdr_type & 0x7f) {
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case PCI_HEADER_TYPE_NORMAL:
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if (class == PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/*
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* read base address registers, again pcibios_fixup() can
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* tweak these
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*/
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pci_read_config_dword(dev, PCI_ROM_ADDRESS, &l);
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dev->rom_address = (l == 0xffffffff) ? 0 : l;
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setup_device(dev, 6);
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/*
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* If this device is on the root bus, there is no bridge
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* to configure, so we can activate it right away.
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*/
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if (!bus->parent_bus)
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pci_register_device(dev);
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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setup_device(dev, 2);
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child_bus = pci_alloc_bus();
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/* inherit parent properties */
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child_bus->host = bus->host;
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child_bus->ops = bus->host->pci_ops;
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child_bus->parent_bus = bus;
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child_bus->resource[PCI_BUS_RESOURCE_MEM] =
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bus->resource[PCI_BUS_RESOURCE_MEM];
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child_bus->resource[PCI_BUS_RESOURCE_MEM_PREF] =
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bus->resource[PCI_BUS_RESOURCE_MEM_PREF];
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child_bus->resource[PCI_BUS_RESOURCE_IO] =
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bus->resource[PCI_BUS_RESOURCE_IO];
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child_bus->parent = &dev->dev;
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child_bus->number = bus_index++;
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child_bus->primary = bus->number;
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list_add_tail(&child_bus->node, &bus->children);
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dev->subordinate = child_bus;
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/* activate bridge device */
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pci_register_device(dev);
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/* scan pci hierarchy behind bridge */
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prescan_setup_bridge(dev);
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pci_scan_bus(child_bus);
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postscan_setup_bridge(dev);
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/* finally active all devices behind the bridge */
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list_for_each_entry(dev, &child_bus->devices, bus_list)
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if (!dev->subordinate)
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pci_register_device(dev);
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break;
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default:
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bad:
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printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
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bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type);
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continue;
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}
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}
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/*
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* We've scanned the bus and so we know all about what's on
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* the other side of any bridges that may be on this bus plus
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* any devices.
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*
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* Return how far we've got finding sub-buses.
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*/
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max = bus_index;
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pr_debug("pci_scan_bus returning with max=%02x\n", max);
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return max;
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}
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static void __pci_set_master(struct pci_dev *dev, bool enable)
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{
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u16 old_cmd, cmd;
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pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
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if (enable)
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cmd = old_cmd | PCI_COMMAND_MASTER;
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else
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cmd = old_cmd & ~PCI_COMMAND_MASTER;
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if (cmd != old_cmd) {
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dev_dbg(&dev->dev, "%s bus mastering\n",
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enable ? "enabling" : "disabling");
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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}
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/**
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* pci_set_master - enables bus-mastering for device dev
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* @dev: the PCI device to enable
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*/
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void pci_set_master(struct pci_dev *dev)
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{
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__pci_set_master(dev, true);
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}
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EXPORT_SYMBOL(pci_set_master);
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/**
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* pci_clear_master - disables bus-mastering for device dev
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* @dev: the PCI device to disable
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*/
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void pci_clear_master(struct pci_dev *dev)
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{
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__pci_set_master(dev, false);
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}
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EXPORT_SYMBOL(pci_clear_master);
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/**
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* pci_enable_device - Initialize device before it's used by a driver.
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* @dev: PCI device to be initialized
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*/
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int pci_enable_device(struct pci_dev *dev)
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{
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u32 t;
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pci_read_config_dword(dev, PCI_COMMAND, &t);
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return pci_write_config_dword(dev, PCI_COMMAND, t
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| PCI_COMMAND_IO
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| PCI_COMMAND_MEMORY
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);
|
|
}
|
|
EXPORT_SYMBOL(pci_enable_device);
|