310 lines
8.9 KiB
C
310 lines
8.9 KiB
C
/*
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* pll.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/am33xx-clock.h>
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#define PRCM_MOD_EN 0x2
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#define PRCM_FORCE_WAKEUP 0x2
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#define PRCM_EMIF_CLK_ACTIVITY (0x1 << 2)
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#define PRCM_L3_GCLK_ACTIVITY (0x1 << 4)
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#define PLL_BYPASS_MODE 0x4
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#define PLL_LOCK_MODE 0x7
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#define PLL_MULTIPLIER_SHIFT 8
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static void interface_clocks_enable(void)
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{
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/* Enable all the Interconnect Modules */
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__raw_writel(PRCM_MOD_EN, CM_PER_L3_CLKCTRL);
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while (__raw_readl(CM_PER_L3_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_L4LS_CLKCTRL);
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while (__raw_readl(CM_PER_L4LS_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_L4FW_CLKCTRL);
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while (__raw_readl(CM_PER_L4FW_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_WKUP_L4WKUP_CLKCTRL);
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while (__raw_readl(CM_WKUP_L4WKUP_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_L3_INSTR_CLKCTRL);
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while (__raw_readl(CM_PER_L3_INSTR_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_L4HS_CLKCTRL);
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while (__raw_readl(CM_PER_L4HS_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
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while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
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/* GPIO0 */
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__raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL);
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while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN);
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/* GPIO1 */
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__raw_writel(PRCM_MOD_EN, CM_PER_GPIO1_CLKCTRL);
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while (__raw_readl(CM_PER_GPIO1_CLKCTRL) != PRCM_MOD_EN);
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/* GPIO2 */
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__raw_writel(PRCM_MOD_EN, CM_PER_GPIO2_CLKCTRL);
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while (__raw_readl(CM_PER_GPIO2_CLKCTRL) != PRCM_MOD_EN);
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/* GPIO3 */
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__raw_writel(PRCM_MOD_EN, CM_PER_GPIO3_CLKCTRL);
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while (__raw_readl(CM_PER_GPIO3_CLKCTRL) != PRCM_MOD_EN);
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}
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static void power_domain_transition_enable(void)
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{
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/*
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* Force power domain wake up transition
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* Ensure that the corresponding interface clock is active before
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* using the peripheral
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*/
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__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3_CLKSTCTRL);
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__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4LS_CLKSTCTRL);
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__raw_writel(PRCM_FORCE_WAKEUP, CM_WKUP_CLKSTCTRL);
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__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L4FW_CLKSTCTRL);
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__raw_writel(PRCM_FORCE_WAKEUP, CM_PER_L3S_CLKSTCTRL);
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}
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/*
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* Enable the module clock and the power domain for required peripherals
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*/
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static void per_clocks_enable(void)
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{
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/* Enable the module clock */
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__raw_writel(PRCM_MOD_EN, CM_PER_TIMER2_CLKCTRL);
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while (__raw_readl(CM_PER_TIMER2_CLKCTRL) != PRCM_MOD_EN);
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/* Select the Master osc 24 MHZ as Timer2 clock source */
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__raw_writel(0x1, CLKSEL_TIMER2_CLK);
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/* UART0 */
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__raw_writel(PRCM_MOD_EN, CM_WKUP_UART0_CLKCTRL);
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while (__raw_readl(CM_WKUP_UART0_CLKCTRL) != PRCM_MOD_EN);
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/* UART1 */
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__raw_writel(PRCM_MOD_EN, CM_PER_UART1_CLKCTRL);
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while (__raw_readl(CM_PER_UART1_CLKCTRL) != PRCM_MOD_EN);
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/* UART2 */
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__raw_writel(PRCM_MOD_EN, CM_PER_UART2_CLKCTRL);
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while (__raw_readl(CM_PER_UART2_CLKCTRL) != PRCM_MOD_EN);
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/* UART3 */
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__raw_writel(PRCM_MOD_EN, CM_PER_UART3_CLKCTRL);
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while (__raw_readl(CM_PER_UART3_CLKCTRL) != PRCM_MOD_EN);
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/* GPMC */
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__raw_writel(PRCM_MOD_EN, CM_PER_GPMC_CLKCTRL);
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while (__raw_readl(CM_PER_GPMC_CLKCTRL) != PRCM_MOD_EN);
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/* ELM */
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__raw_writel(PRCM_MOD_EN, CM_PER_ELM_CLKCTRL);
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while (__raw_readl(CM_PER_ELM_CLKCTRL) != PRCM_MOD_EN);
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/* i2c0 */
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__raw_writel(PRCM_MOD_EN, CM_WKUP_I2C0_CLKCTRL);
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while (__raw_readl(CM_WKUP_I2C0_CLKCTRL) != PRCM_MOD_EN);
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/* i2c1 */
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__raw_writel(PRCM_MOD_EN, CM_PER_I2C1_CLKCTRL);
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while (__raw_readl(CM_PER_I2C1_CLKCTRL) != PRCM_MOD_EN);
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/* i2c2 */
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__raw_writel(PRCM_MOD_EN, CM_PER_I2C2_CLKCTRL);
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while (__raw_readl(CM_PER_I2C2_CLKCTRL) != PRCM_MOD_EN);
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/* Ethernet */
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__raw_writel(PRCM_MOD_EN, CM_PER_CPGMAC0_CLKCTRL);
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__raw_writel(PRCM_MOD_EN, CM_PER_CPSW_CLKSTCTRL);
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while ((__raw_readl(CM_PER_CPGMAC0_CLKCTRL) & 0x30000) != 0x0);
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/* MMC 0 & 1 */
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__raw_writel(PRCM_MOD_EN, CM_PER_MMC0_CLKCTRL);
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while (__raw_readl(CM_PER_MMC0_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_MMC1_CLKCTRL);
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while (__raw_readl(CM_PER_MMC1_CLKCTRL) != PRCM_MOD_EN);
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/* Enable the control module though RBL would have done it*/
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__raw_writel(PRCM_MOD_EN, CM_WKUP_CONTROL_CLKCTRL);
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while (__raw_readl(CM_WKUP_CONTROL_CLKCTRL) != PRCM_MOD_EN);
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/* SPI 0 & 1 */
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__raw_writel(PRCM_MOD_EN, CM_PER_SPI0_CLKCTRL);
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while (__raw_readl(CM_PER_SPI0_CLKCTRL) != PRCM_MOD_EN);
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__raw_writel(PRCM_MOD_EN, CM_PER_SPI1_CLKCTRL);
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while (__raw_readl(CM_PER_SPI1_CLKCTRL) != PRCM_MOD_EN);
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}
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static void mpu_pll_config(int mpupll_M, int osc)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = __raw_readl(CM_CLKMODE_DPLL_MPU);
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clksel = __raw_readl(CM_CLKSEL_DPLL_MPU);
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div_m2 = __raw_readl(CM_DIV_M2_DPLL_MPU);
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/* Set the PLL to bypass Mode */
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__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_MPU);
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while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((mpupll_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_MPU);
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div_m2 = div_m2 & ~0x1f;
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div_m2 = div_m2 | MPUPLL_M2;
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__raw_writel(div_m2, CM_DIV_M2_DPLL_MPU);
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clkmode = clkmode | 0x7;
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__raw_writel(clkmode, CM_CLKMODE_DPLL_MPU);
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while(__raw_readl(CM_IDLEST_DPLL_MPU) != 0x1);
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}
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static void core_pll_config(int osc)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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clkmode = __raw_readl(CM_CLKMODE_DPLL_CORE);
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clksel = __raw_readl(CM_CLKSEL_DPLL_CORE);
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div_m4 = __raw_readl(CM_DIV_M4_DPLL_CORE);
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div_m5 = __raw_readl(CM_DIV_M5_DPLL_CORE);
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div_m6 = __raw_readl(CM_DIV_M6_DPLL_CORE);
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/* Set the PLL to bypass Mode */
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__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_CORE);
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while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((COREPLL_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_CORE);
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div_m4 = div_m4 & ~0x1f;
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div_m4 = div_m4 | COREPLL_M4;
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__raw_writel(div_m4, CM_DIV_M4_DPLL_CORE);
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div_m5 = div_m5 & ~0x1f;
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div_m5 = div_m5 | COREPLL_M5;
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__raw_writel(div_m5, CM_DIV_M5_DPLL_CORE);
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div_m6 = div_m6 & ~0x1f;
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div_m6 = div_m6 | COREPLL_M6;
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__raw_writel(div_m6, CM_DIV_M6_DPLL_CORE);
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clkmode = clkmode | 0x7;
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__raw_writel(clkmode, CM_CLKMODE_DPLL_CORE);
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while(__raw_readl(CM_IDLEST_DPLL_CORE) != 0x1);
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}
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static void per_pll_config(int osc)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = __raw_readl(CM_CLKMODE_DPLL_PER);
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clksel = __raw_readl(CM_CLKSEL_DPLL_PER);
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div_m2 = __raw_readl(CM_DIV_M2_DPLL_PER);
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/* Set the PLL to bypass Mode */
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__raw_writel(PLL_BYPASS_MODE, CM_CLKMODE_DPLL_PER);
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((PERPLL_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_PER);
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div_m2 = div_m2 & ~0x7f;
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div_m2 = div_m2 | PERPLL_M2;
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__raw_writel(div_m2, CM_DIV_M2_DPLL_PER);
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clkmode = clkmode | 0x7;
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__raw_writel(clkmode, CM_CLKMODE_DPLL_PER);
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while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1);
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}
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static void ddr_pll_config(int osc, int ddrpll_M)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = __raw_readl(CM_CLKMODE_DPLL_DDR);
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clksel = __raw_readl(CM_CLKSEL_DPLL_DDR);
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div_m2 = __raw_readl(CM_DIV_M2_DPLL_DDR);
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/* Set the PLL to bypass Mode */
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clkmode = (clkmode & 0xfffffff8) | 0x00000004;
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__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100);
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clksel = clksel & (~0x7ffff);
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clksel = clksel | ((ddrpll_M << 0x8) | (osc - 1));
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__raw_writel(clksel, CM_CLKSEL_DPLL_DDR);
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div_m2 = div_m2 & 0xFFFFFFE0;
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div_m2 = div_m2 | DDRPLL_M2;
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__raw_writel(div_m2, CM_DIV_M2_DPLL_DDR);
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clkmode = (clkmode & 0xfffffff8) | 0x7;
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__raw_writel(clkmode, CM_CLKMODE_DPLL_DDR);
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
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}
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void enable_ddr_clocks(void)
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{
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/* Enable the EMIF_FW Functional clock */
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__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
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/* Enable EMIF0 Clock */
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__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_CLKCTRL);
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/* Poll for emif_gclk & L3_G clock are active */
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while ((__raw_readl(CM_PER_L3_CLKSTCTRL) & (PRCM_EMIF_CLK_ACTIVITY |
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PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
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PRCM_L3_GCLK_ACTIVITY));
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/* Poll if module is functional */
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while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN);
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}
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/*
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* Configure the PLL/PRCM for necessary peripherals
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*/
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void pll_init(int mpupll_M, int osc, int ddrpll_M)
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{
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mpu_pll_config(mpupll_M, osc);
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core_pll_config(osc);
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per_pll_config(osc);
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ddr_pll_config(osc, ddrpll_M);
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/* Enable the required interconnect clocks */
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interface_clocks_enable();
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/* Enable power domain transition */
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power_domain_transition_enable();
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/* Enable the required peripherals */
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per_clocks_enable();
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}
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