147 lines
5.2 KiB
C
147 lines
5.2 KiB
C
/**
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* @file
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* @brief This file contains the processor specific definitions of
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* the TI OMAP34XX. For more info on OMAP34XX,
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* See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf
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*
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* OMAP34XX base address defines go here.
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*
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* Originally from Linux kernel:
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* http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
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* include/asm-arm/arch-omap/omap3-silicon.h
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*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, <www.ti.com>
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* Copyright (C) 2007 Nokia Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_OMAP3_H
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#define __ASM_ARCH_OMAP3_H
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/* PLEASE PLACE ONLY BASE DEFINES HERE */
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/** OMAP Internal Bus Base addresses */
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#define OMAP3_L4_CORE_BASE 0x48000000
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#define OMAP3_INTC_BASE 0x48200000
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#define OMAP3_L4_WKUP_BASE 0x48300000
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#define OMAP3_L4_PER_BASE 0x49000000
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#define OMAP3_L4_EMU_BASE 0x54000000
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#define OMAP3_SGX_BASE 0x50000000
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#define OMAP3_IVA_BASE 0x5C000000
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#define OMAP3_SMX_APE_BASE 0x68000000
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#define OMAP3_SMS_BASE 0x6C000000
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#define OMAP3_SDRC_BASE 0x6D000000
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#define OMAP3_GPMC_BASE 0x6E000000
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/** Peripheral Base Addresses */
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#define OMAP3_CTRL_BASE (OMAP3_L4_CORE_BASE + 0x02000)
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#define OMAP3_CM_BASE (OMAP3_L4_CORE_BASE + 0x04000)
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#define OMAP3_PRM_BASE (OMAP3_L4_WKUP_BASE + 0x06000)
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#define OMAP3_UART1_BASE (OMAP3_L4_CORE_BASE + 0x6A000)
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#define OMAP3_UART2_BASE (OMAP3_L4_CORE_BASE + 0x6C000)
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#define OMAP3_UART3_BASE (OMAP3_L4_PER_BASE + 0x20000)
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#define OMAP3_I2C1_BASE (OMAP3_L4_CORE_BASE + 0x70000)
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#define OMAP3_I2C2_BASE (OMAP3_L4_CORE_BASE + 0x72000)
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#define OMAP3_I2C3_BASE (OMAP3_L4_CORE_BASE + 0x60000)
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#define OMAP3_GPTIMER1_BASE (OMAP3_L4_WKUP_BASE + 0x18000)
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#define OMAP3_GPTIMER2_BASE (OMAP3_L4_PER_BASE + 0x32000)
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#define OMAP3_GPTIMER3_BASE (OMAP3_L4_PER_BASE + 0x34000)
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#define OMAP3_GPTIMER4_BASE (OMAP3_L4_PER_BASE + 0x36000)
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#define OMAP3_GPTIMER5_BASE (OMAP3_L4_PER_BASE + 0x38000)
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#define OMAP3_GPTIMER6_BASE (OMAP3_L4_PER_BASE + 0x3A000)
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#define OMAP3_GPTIMER7_BASE (OMAP3_L4_PER_BASE + 0x3C000)
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#define OMAP3_GPTIMER8_BASE (OMAP3_L4_PER_BASE + 0x3E000)
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#define OMAP3_GPTIMER9_BASE (OMAP3_L4_PER_BASE + 0x40000)
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#define OMAP3_GPTIMER10_BASE (OMAP3_L4_CORE_BASE + 0x86000)
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#define OMAP3_GPTIMER11_BASE (OMAP3_L4_CORE_BASE + 0x88000)
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#define OMAP3_WDTIMER2_BASE (OMAP3_L4_WKUP_BASE + 0x14000)
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#define OMAP3_WDTIMER3_BASE (OMAP3_L4_PER_BASE + 0x30000)
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#define OMAP3_32KTIMER_BASE (OMAP3_L4_WKUP_BASE + 0x20000)
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#define OMAP3_MMC1_BASE (OMAP3_L4_CORE_BASE + 0x9C000)
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#define OMAP3_MMC2_BASE (OMAP3_L4_CORE_BASE + 0xB4000)
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#define OMAP3_MMC3_BASE (OMAP3_L4_CORE_BASE + 0xAD000)
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#define OMAP3_MUSB0_BASE (OMAP3_L4_CORE_BASE + 0xAB000)
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#define OMAP3_GPIO1_BASE (OMAP3_L4_WKUP_BASE + 0x10000)
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#define OMAP3_GPIO2_BASE (OMAP3_L4_PER_BASE + 0x50000)
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#define OMAP3_GPIO3_BASE (OMAP3_L4_PER_BASE + 0x52000)
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#define OMAP3_GPIO4_BASE (OMAP3_L4_PER_BASE + 0x54000)
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#define OMAP3_GPIO5_BASE (OMAP3_L4_PER_BASE + 0x56000)
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#define OMAP3_GPIO6_BASE (OMAP3_L4_PER_BASE + 0x58000)
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/** MPU WDT Definition */
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#define OMAP3_MPU_WDTIMER_BASE OMAP3_WDTIMER2_BASE
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#define OMAP3_HSUSB_OTG_BASE (OMAP3_L4_CORE_BASE + 0xAB000)
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#define OMAP3_USBTLL_BASE (OMAP3_L4_CORE_BASE + 0x62000)
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#define OMAP3_UHH_CONFIG_BASE (OMAP3_L4_CORE_BASE + 0x64000)
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#define OMAP3_OHCI_BASE (OMAP3_L4_CORE_BASE + 0x64400)
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#define OMAP3_EHCI_BASE (OMAP3_L4_CORE_BASE + 0x64800)
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/** Interrupt Vector base address */
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#define OMAP3_SRAM_BASE 0x40200000
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#define OMAP3_SRAM_SCRATCH_SPACE 0x4020f000 /* start of public stack */
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#define OMAP3_SRAM_INTVECT 0x4020F800
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#define OMAP3_SRAM_INTVECT_COPYSIZE 0x64
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/** Gives the silicon revision */
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#define OMAP3_TAP_BASE (OMAP3_L4_WKUP_BASE + 0xA000)
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#define OMAP3_IDCODE_REG (OMAP3_TAP_BASE + 0x204)
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#define OMAP3_DIE_ID_0 (OMAP3_TAP_BASE + 0x218)
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#define OMAP3_DIE_ID_1 (OMAP3_TAP_BASE + 0x21c)
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#define OMAP3_DIE_ID_2 (OMAP3_TAP_BASE + 0x220)
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#define OMAP3_DIE_ID_3 (OMAP3_TAP_BASE + 0x224)
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/** Masks to extract information from ID code register */
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#define IDCODE_HAWKEYE_MASK 0x0FFFF000
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#define IDCODE_VERSION_MASK 0xF0000000
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#define get_hawkeye(v) (((v) & IDCODE_HAWKEYE_MASK) >> 12)
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#define get_version(v) (((v) & IDCODE_VERSION_MASK) >> 28)
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#define HAWKEYE_ES1 0x0B6D6000
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#define HAWKEYE_ES2 0x0B7AE000
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#define HAWKEYE_ES2_1 0x1B7AE000
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#define DEVICE_MASK ((0x1 << 8)|(0x1 << 9)|(0x1 << 10))
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#define OMAP_SDRC_CS0 0x80000000
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#define OMAP_SDRC_CS1 0xA0000000
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/* PRM */
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#define OMAP3_PRM_RSTCTRL_RESET 0x04
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/*
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* ROM code API related flags
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*/
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#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
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#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
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/* If Architecture specific init functions are present */
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#ifndef __ASSEMBLY__
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void omap3_core_init(void);
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void omap3_gp_romcode_call(u32 service_id, u32 parameter);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_OMAP3_H */
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