323 lines
8.4 KiB
ArmAsm
323 lines
8.4 KiB
ArmAsm
/*
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* Board specific setup info
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/hardware.h>
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#define SDRAM 0x20000000 /* address of the SDRAM */
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/* values */
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/* clocks */
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#define MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */
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#define PLLAR_VAL (0x2000BF00 | ((MASTER_PLL_MUL - 1)<< 16) | (MASTER_PLL_DIV))
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/* #define PLLAR_VAL 0x200CBF01 */ /* 239.616000 MHz for PCK */
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#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB) */
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#define MCKR1_VAL 0x00000100 /* PCK/2 = MCK Master Clock from PLLA*/
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#define MCKR2_VAL 0x00000102 /* PCK/2 = MCK Master Clock from PLLA*/
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#define WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */
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#define PIOD_PDR_VAL1 0xFFFF0000 /* define PDC[31:16] as DATA[31:16] */
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#define PIOD_PPUDR_VAL 0xFFFF0000 /* no pull-up for D[31:16] */
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#define MATRIX_EBI0CSA_VAL 0x0001010A /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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/*#define MATRIX_EBI1CSA_VAL 0x00000000 /* EBI1_CSA, 1.8V memory*/
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#define MATRIX_EBI1CSA_VAL 0x00010100 /* EBI1_CSA, 3.3v, no pull-ups*/
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/* SDRAM */
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#define SDRC_MR_VAL1 0 /* SDRAMC_MR Mode register */
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#define SDRC_TR_VAL1 0x13C /* SDRAMC_TR - Refresh Timer register*/
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/*#define SDRC_CR_VAL 0x85237279*/ /* SDRAMC_CR - Configuration register*/
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/*#define SDRC_CR_VAL 0x85227259 CL2 */
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#define SDRC_CR_VAL 0x85227279 /*CL3*/
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#define SDRC_MDR_VAL 0 /* Memory Device Register -> SDRAM */
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#define SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */
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#define SDRAM_VAL1 0 /* SDRAM_BASE */
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#define SDRC_MR_VAL3 4 /* SDRC_MR */
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#define SDRAM_VAL2 0 /* SDRAM_BASE */
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#define SDRAM_VAL3 0 /* SDRAM_BASE */
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#define SDRAM_VAL4 0 /* SDRAM_BASE */
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#define SDRAM_VAL5 0 /* SDRAM_BASE */
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#define SDRAM_VAL6 0 /* SDRAM_BASE */
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#define SDRAM_VAL7 0 /* SDRAM_BASE */
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#define SDRAM_VAL8 0 /* SDRAM_BASE */
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#define SDRAM_VAL9 0 /* SDRAM_BASE */
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#define SDRC_MR_VAL4 3 /* SDRC_MR */
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#define SDRAM_VAL10 0 /* SDRAM_BASE */
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#define SDRC_MR_VAL5 0 /* SDRC_MR */
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#define SDRAM_VAL11 0 /* SDRAM_BASE */
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#define SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup CS0 (NOR Flash) - 16-bit, 15 WS */
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#define SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */
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#define SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */
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#define SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */
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#define SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */
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#define RSTC_RMR_VAL 0xA5000301 /* user reset enable */
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#define MASTER_PLL_MUL 162
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#define MASTER_PLL_DIV 15
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_TEXT_BASE:
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.word TEXT_BASE
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r5, pc // r5 = POS1 + 4 current
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POS1:
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ldr r0, =POS1 // r0 = POS1 compile
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ldr r2, _TEXT_BASE
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sub r0, r0, r2 // r0 = POS1-_TEXT_BASE (POS1 relative)
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sub r5, r5, r0 // r0 = TEXT_BASE-1
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sub r5, r5, #4 // r1 = text base - current
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/* memory control configuration 1 */
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ldr r0, =SMRDATA
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ldr r2, =SMRDATA1
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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sub r2, r2, r1
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add r0, r0, r5
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add r2, r2, r5
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0:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 0b
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/*-----------------------------------------------------------------------------
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;PMC Init Step 1.
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;------------------------------------------------------------------------------
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;- Enable the Main Oscillator
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;----------------------------------------------------------------------------*/
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/* Test if main oscillator is enabled */
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ldr r0,=AT91C_PMC_SR
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ldr r1, [r0]
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ldr r2,=AT91C_PMC_MOSCS
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ands r1, r1, r2
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ldr r1, =AT91C_CKGR_MOR
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/* Main oscillator Enable register PMC_MOR: */
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/* Enable main oscillator, OSCOUNT = 0xFF */
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ldr r0, =0x0000FF01
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str r0, [r1]
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/* Reading the PMC Status register to detect when the */
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/* Main Oscillator is enabled */
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mov r4, #AT91C_PMC_MOSCS
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ldr r0,=AT91C_PMC_SR
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MOSCS_Loop:
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ldr r3, [r0]
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and r3, r4, r3
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cmp r3, #AT91C_PMC_MOSCS
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bne MOSCS_Loop
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/*-----------------------------------------------------------------------------
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;PMC Init Step 2.
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;------------------------------------------------------------------------------
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;- Setup PLLA
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;----------------------------------------------------------------------------*/
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ldr r1, =AT91C_CKGR_PLLAR
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/* (18.432 MHz / 1) * 13 = 239 MHz */
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ldr r0, =PLLAR_VAL
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str r0, [r1]
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/* Reading the PMC Status register to detect */
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/* when the PLLA is locked */
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mov r4, #AT91C_PMC_LOCKA
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ldr r0,=AT91C_PMC_SR
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MOSCS_Loop1:
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ldr r3, [r0]
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and r3, r4, r3
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cmp r3, #AT91C_PMC_LOCKA
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bne MOSCS_Loop1
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/*-----------------------------------------------------------------------------
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;PMC Init Step 3.
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;------------------------------------------------------------------------------
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;- Switch on the Main Oscillator 18.432 MHz
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;----------------------------------------------------------------------------*/
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Init_MCKR:
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/* -Master Clock Controller register PMC_MCKR */
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ldr r0, =0x100
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ldr r1, =AT91C_PMC_MCKR
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str r0, [r1]
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/* Reading the PMC Status register to detect */
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/* when the Master clock is ready */
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mov r4, #AT91C_PMC_MCKRDY
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MCKRDY_Loop:
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ldr r1, =AT91C_PMC_SR
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ldr r3, [r1]
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and r3, r4, r3
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cmp r3, #AT91C_PMC_MCKRDY
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bne MCKRDY_Loop
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ldr r0, =0x102
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ldr r1, =AT91C_PMC_MCKR
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str r0, [r1]
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/* Reading the PMC Status register to detect */
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/* when the Master clock is ready */
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mov r4, #AT91C_PMC_MCKRDY
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MCKRDY_Loop1:
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ldr r1, =AT91C_PMC_SR
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ldr r3, [r1]
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and r3, r4, r3
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cmp r3, #AT91C_PMC_MCKRDY
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bne MCKRDY_Loop1
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/*-----------------------------------------------------------------------------
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;PMC Init Step 4.
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;------------------------------------------------------------------------------
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;- Setup PLLB
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;----------------------------------------------------------------------------*/
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ldr r1, = AT91C_PMC_PLLBR
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/* 48.054857 MHz = 18432000 * 72 / 14 / 2 for USB) */
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ldr r0, =PLLBR_VAL
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str r0, [r1]
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/* Reading the PMC Status register to detect */
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/* when the PLLB is locked */
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mov r4, #AT91C_PMC_LOCKB
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MOSCS_Loop2:
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ldr r1, = AT91C_PMC_SR
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ldr r3, [r1]
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and r3, r4, r3
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cmp r3, #AT91C_PMC_LOCKB
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bne MOSCS_Loop2
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/* memory control configuration 2 */
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ldr r0, =SMRDATA1
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ldr r2, =SMRDATA2
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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sub r2, r2, r1
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add r0, r0, r5
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add r2, r2, r5
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2:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 2b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word AT91C_WDTC_WDMR
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.word WDTC_WDMR_VAL
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.word AT91C_PIOD_PDR
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.word PIOD_PDR_VAL1
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.word AT91C_PIOD_PPUDR
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.word PIOD_PPUDR_VAL
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.word AT91C_PIOD_ASR
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.word PIOD_PPUDR_VAL
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.word AT91C_CCFG_EBI0CSA
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.word MATRIX_EBI0CSA_VAL
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.word AT91C_CCFG_EBI1CSA
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.word MATRIX_EBI1CSA_VAL
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/* flash */
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.word AT91C_SMC0_CTRL0
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.word SMC0_CTRL0_VAL
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.word AT91C_SMC0_CYCLE0
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.word SMC0_CYCLE0_VAL
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.word AT91C_SMC0_PULSE0
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.word SMC0_PULSE0_VAL
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.word AT91C_SMC0_SETUP0
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.word SMC0_SETUP0_VAL
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SMRDATA1:
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.word AT91C_SDRAMC0_MR
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.word SDRC_MR_VAL1
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.word AT91C_SDRAMC0_TR
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.word SDRC_TR_VAL1
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.word AT91C_SDRAMC0_CR
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.word SDRC_CR_VAL
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.word AT91C_SDRAMC0_MDR
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.word SDRC_MDR_VAL
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.word AT91C_SDRAMC0_MR
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.word SDRC_MR_VAL2
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.word SDRAM
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.word SDRAM_VAL1
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.word AT91C_SDRAMC0_MR
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.word SDRC_MR_VAL3
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.word SDRAM
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.word SDRAM_VAL2
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.word SDRAM
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.word SDRAM_VAL3
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.word SDRAM
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.word SDRAM_VAL4
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.word SDRAM
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.word SDRAM_VAL5
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.word SDRAM
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.word SDRAM_VAL6
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.word SDRAM
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.word SDRAM_VAL7
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.word SDRAM
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.word SDRAM_VAL8
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.word SDRAM
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.word SDRAM_VAL9
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.word AT91C_SDRAMC0_MR
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.word SDRC_MR_VAL4
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.word SDRAM
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.word SDRAM_VAL10
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.word AT91C_SDRAMC0_MR
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.word SDRC_MR_VAL5
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.word SDRAM
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.word SDRAM_VAL11
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.word AT91C_SDRAMC0_TR
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.word SDRC_TR_VAL2
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.word SDRAM
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.word SDRAM_VAL12
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/* User reset enable*/
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.word AT91C_RSTC_RMR
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.word RSTC_RMR_VAL
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/* MATRIX_MCFG - REMAP all masters */
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SMRDATA2:
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.word 0
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