229 lines
4.8 KiB
ArmAsm
229 lines
4.8 KiB
ArmAsm
#include <config.h>
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#include <linux/linkage.h>
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#include <asm-generic/memory_layout.h>
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/*
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*************************************************************************
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*
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* Interrupt handling
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*
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*************************************************************************
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*/
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72
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#define S_OLD_R0 68
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#define S_PSR 64
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#define S_PC 60
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#define S_LR 56
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#define S_SP 52
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#define S_IP 48
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#define S_FP 44
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#define S_R10 40
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#define S_R9 36
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#define S_R8 32
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#define S_R7 28
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#define S_R6 24
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#define S_R5 20
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#define S_R4 16
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#define S_R3 12
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#define S_R2 8
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#define S_R1 4
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#define S_R0 0
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#define MODE_SVC 0x13
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/*
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* use bad_save_user_regs for abort/prefetch/undef/swi ...
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
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*/
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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ldr r2, =abort_stack
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ldmia r2, {r2 - r3} @ get pc, cpsr
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add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
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add r5, sp, #S_SP
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mov r1, lr
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp
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.endm
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp
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.endm
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0
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ldr lr, [sp, #S_PC] @ Get PC
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add sp, sp, #S_FRAME_SIZE
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm
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.macro get_bad_stack
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ldr r13, =abort_stack
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str lr, [r13] @ save caller lr / spsr
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mrs lr, spsr
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str lr, [r13, #4]
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mov r13, #MODE_SVC @ prepare SVC-Mode
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@ msr spsr_c, r13
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msr spsr, r13
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mov lr, pc
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movs pc, lr
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.endm
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.macro try_data_abort
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ldr r13, =arm_ignore_data_abort @ check try mode
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ldr r13, [r13]
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cmp r13, #0
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beq do_abort_\@
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ldr r13, =arm_data_abort_occurred
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str r13, [r13]
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mrs r13, spsr @ read saved CPSR
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tst r13, #1<<5 @ check Thumb mode
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subeq lr, #4 @ next ARM instr
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subne lr, #6 @ next Thumb instr
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movs pc, lr
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do_abort_\@:
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.endm
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START
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.endm
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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/*
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* exception handlers
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*/
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.section ".text","ax"
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.arm
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.align 5
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undefined_instruction:
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get_bad_stack
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bad_save_user_regs
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bl do_undefined_instruction
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.align 5
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software_interrupt:
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get_bad_stack
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bad_save_user_regs
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bl do_software_interrupt
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.align 5
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prefetch_abort:
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get_bad_stack
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bad_save_user_regs
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bl do_prefetch_abort
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.align 5
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data_abort:
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try_data_abort
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get_bad_stack
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bad_save_user_regs
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bl do_data_abort
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.align 5
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irq:
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get_bad_stack
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bad_save_user_regs
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bl do_irq
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.align 5
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fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_ARM_EXCEPTIONS)
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/*
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* With relocatable binary support the runtime exception vectors do not match
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* the addresses in the binary. We have to fix them up during runtime
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*/
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ENTRY(arm_fixup_vectors)
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ldr r0, =undefined_instruction
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ldr r1, =_undefined_instruction
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str r0, [r1]
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ldr r0, =software_interrupt
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ldr r1, =_software_interrupt
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str r0, [r1]
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ldr r0, =prefetch_abort
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ldr r1, =_prefetch_abort
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str r0, [r1]
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ldr r0, =data_abort
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ldr r1, =_data_abort
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str r0, [r1]
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ldr r0, =irq
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ldr r1, =_irq
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str r0, [r1]
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ldr r0, =fiq
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ldr r1, =_fiq
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str r0, [r1]
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bx lr
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ENDPROC(arm_fixup_vectors)
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#endif
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.section .text_exceptions
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.globl extable
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extable:
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1: b 1b /* barebox_arm_reset_vector */
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#ifdef CONFIG_ARM_EXCEPTIONS
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ldr pc, _undefined_instruction /* undefined instruction */
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ldr pc, _software_interrupt /* software interrupt (SWI) */
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ldr pc, _prefetch_abort /* prefetch abort */
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ldr pc, _data_abort /* data abort */
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1: b 1b /* (reserved) */
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ldr pc, _irq /* irq (interrupt) */
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ldr pc, _fiq /* fiq (fast interrupt) */
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.globl _undefined_instruction
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_undefined_instruction: .word undefined_instruction
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.globl _software_interrupt
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_software_interrupt: .word software_interrupt
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.globl _prefetch_abort
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_prefetch_abort: .word prefetch_abort
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.globl _data_abort
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_data_abort: .word data_abort
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.globl _irq
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_irq: .word irq
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.globl _fiq
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_fiq: .word fiq
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#else
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1: b 1b /* undefined instruction */
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1: b 1b /* software interrupt (SWI) */
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1: b 1b /* prefetch abort */
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1: b 1b /* data abort */
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1: b 1b /* (reserved) */
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1: b 1b /* irq (interrupt) */
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1: b 1b /* fiq (fast interrupt) */
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#endif
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.section .data
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.align 4
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.global arm_ignore_data_abort
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arm_ignore_data_abort:
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.word arm_ignore_data_abort /* When != 0 data aborts are ignored */
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.global arm_data_abort_occurred
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arm_data_abort_occurred:
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.word arm_data_abort_occurred /* set != 0 by the data abort handler */
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abort_stack:
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.space 8
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