91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
/*
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* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/compiler.h>
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#include "mach/tegra20-car.h"
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#include "mach/lowlevel.h"
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static __always_inline
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void tegra_dvc_init(void)
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{
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int div;
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u32 reg;
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/* reset DVC controller and enable clock */
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writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET);
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
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reg |= CRC_CLK_OUT_ENB_H_DVC;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
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/* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */
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div = ((tegra_get_osc_clock() * 3) >> 22) - 1;
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writel((div) | (3 << 30),
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TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC);
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/* clear DVC reset */
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tegra_ll_delay_usec(3);
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writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
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}
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#define TEGRA_I2C_CNFG 0x00
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#define TEGRA_I2C_CMD_ADDR0 0x04
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#define TEGRA_I2C_CMD_DATA1 0x0c
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#define TEGRA_I2C_SEND_2_BYTES 0x0a02
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static __always_inline
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void tegra_dvc_write_addr(u32 addr, u32 config)
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{
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writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0);
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writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
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}
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static __always_inline
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void tegra_dvc_write_data(u32 data, u32 config)
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{
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writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1);
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writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
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}
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static __always_inline
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void tegra30_tps65911_cpu_rail_enable(void)
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{
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tegra_dvc_write_addr(0x5a, 2);
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/* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */
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tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES);
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tegra_ll_delay_usec(1000);
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/* reg 27, VDDctrl enable */
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tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
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tegra_ll_delay_usec(10 * 1000);
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}
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static __always_inline
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void tegra30_tps62366a_ramp_vddcore(void)
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{
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tegra_dvc_write_addr(0xc0, 2);
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/* set VDDcore to 1,2V */
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tegra_dvc_write_data(0x4601, TEGRA_I2C_SEND_2_BYTES);
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tegra_ll_delay_usec(1000);
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}
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static __always_inline
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void tegra30_tps62361b_ramp_vddcore(void)
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{
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tegra_dvc_write_addr(0xc0, 2);
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/* set VDDcore to 1,2V */
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tegra_dvc_write_data(0x4603, TEGRA_I2C_SEND_2_BYTES);
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tegra_ll_delay_usec(1000);
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}
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