201 lines
5.2 KiB
C
201 lines
5.2 KiB
C
/*
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* Based on the Linux Tegra clock code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <linux/clk.h>
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#include <linux/reset-controller.h>
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#include <mach/lowlevel.h>
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#include "clk.h"
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#define CLK_OUT_ENB_L 0x010
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#define CLK_OUT_ENB_H 0x014
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#define CLK_OUT_ENB_U 0x018
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#define CLK_OUT_ENB_V 0x360
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#define CLK_OUT_ENB_W 0x364
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#define CLK_OUT_ENB_X 0x280
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#define CLK_OUT_ENB_SET_L 0x320
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#define CLK_OUT_ENB_CLR_L 0x324
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#define CLK_OUT_ENB_SET_H 0x328
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#define CLK_OUT_ENB_CLR_H 0x32c
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#define CLK_OUT_ENB_SET_U 0x330
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#define CLK_OUT_ENB_CLR_U 0x334
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#define CLK_OUT_ENB_SET_V 0x440
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#define CLK_OUT_ENB_CLR_V 0x444
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#define CLK_OUT_ENB_SET_W 0x448
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#define CLK_OUT_ENB_CLR_W 0x44c
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#define CLK_OUT_ENB_SET_X 0x284
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#define CLK_OUT_ENB_CLR_X 0x288
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#define RST_DEVICES_L 0x004
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#define RST_DEVICES_H 0x008
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#define RST_DEVICES_U 0x00C
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#define RST_DFLL_DVCO 0x2F4
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#define RST_DEVICES_V 0x358
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#define RST_DEVICES_W 0x35C
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#define RST_DEVICES_X 0x28C
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#define RST_DEVICES_SET_L 0x300
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#define RST_DEVICES_CLR_L 0x304
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#define RST_DEVICES_SET_H 0x308
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#define RST_DEVICES_CLR_H 0x30c
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#define RST_DEVICES_SET_U 0x310
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#define RST_DEVICES_CLR_U 0x314
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#define RST_DEVICES_SET_V 0x430
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#define RST_DEVICES_CLR_V 0x434
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#define RST_DEVICES_SET_W 0x438
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#define RST_DEVICES_CLR_W 0x43c
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#define RST_DEVICES_SET_X 0x290
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#define RST_DEVICES_CLR_X 0x294
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static struct tegra_clk_periph_regs periph_regs[] = {
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[0] = {
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.enb_reg = CLK_OUT_ENB_L,
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.enb_set_reg = CLK_OUT_ENB_SET_L,
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.enb_clr_reg = CLK_OUT_ENB_CLR_L,
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.rst_reg = RST_DEVICES_L,
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.rst_set_reg = RST_DEVICES_SET_L,
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.rst_clr_reg = RST_DEVICES_CLR_L,
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},
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[1] = {
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.enb_reg = CLK_OUT_ENB_H,
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.enb_set_reg = CLK_OUT_ENB_SET_H,
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.enb_clr_reg = CLK_OUT_ENB_CLR_H,
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.rst_reg = RST_DEVICES_H,
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.rst_set_reg = RST_DEVICES_SET_H,
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.rst_clr_reg = RST_DEVICES_CLR_H,
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},
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[2] = {
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.enb_reg = CLK_OUT_ENB_U,
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.enb_set_reg = CLK_OUT_ENB_SET_U,
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.enb_clr_reg = CLK_OUT_ENB_CLR_U,
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.rst_reg = RST_DEVICES_U,
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.rst_set_reg = RST_DEVICES_SET_U,
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.rst_clr_reg = RST_DEVICES_CLR_U,
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},
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[3] = {
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.enb_reg = CLK_OUT_ENB_V,
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.enb_set_reg = CLK_OUT_ENB_SET_V,
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.enb_clr_reg = CLK_OUT_ENB_CLR_V,
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.rst_reg = RST_DEVICES_V,
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.rst_set_reg = RST_DEVICES_SET_V,
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.rst_clr_reg = RST_DEVICES_CLR_V,
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},
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[4] = {
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.enb_reg = CLK_OUT_ENB_W,
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.enb_set_reg = CLK_OUT_ENB_SET_W,
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.enb_clr_reg = CLK_OUT_ENB_CLR_W,
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.rst_reg = RST_DEVICES_W,
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.rst_set_reg = RST_DEVICES_SET_W,
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.rst_clr_reg = RST_DEVICES_CLR_W,
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},
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[5] = {
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.enb_reg = CLK_OUT_ENB_X,
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.enb_set_reg = CLK_OUT_ENB_SET_X,
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.enb_clr_reg = CLK_OUT_ENB_CLR_X,
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.rst_reg = RST_DEVICES_X,
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.rst_set_reg = RST_DEVICES_SET_X,
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.rst_clr_reg = RST_DEVICES_CLR_X,
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},
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};
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static void __iomem *car_base;
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void tegra_init_from_table(struct tegra_clk_init_table *tbl,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; tbl->clk_id < clk_max; tbl++) {
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clk = clks[tbl->clk_id];
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if (!clk)
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return;
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if (tbl->parent_id < clk_max) {
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struct clk *parent = clks[tbl->parent_id];
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if (clk_set_parent(clk, parent)) {
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pr_err("%s: Failed to set parent %s of %s\n",
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__func__, parent->name, clk->name);
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WARN_ON(1);
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}
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}
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if (tbl->rate)
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if (clk_set_rate(clk, tbl->rate)) {
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pr_err("%s: Failed to set rate %lu of %s\n",
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__func__, tbl->rate, clk->name);
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WARN_ON(1);
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}
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if (tbl->state)
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if (clk_enable(clk)) {
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pr_err("%s: Failed to enable %s\n", __func__,
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clk->name);
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WARN_ON(1);
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}
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}
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}
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static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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tegra_read_chipid();
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writel(BIT(id % 32), car_base + periph_regs[id / 32].rst_set_reg);
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return 0;
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}
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static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel(BIT(id % 32), car_base + periph_regs[id / 32].rst_clr_reg);
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return 0;
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}
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static struct reset_control_ops rst_ops = {
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.assert = tegra_clk_rst_assert,
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.deassert = tegra_clk_rst_deassert,
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};
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static struct reset_controller_dev rst_ctlr = {
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.ops = &rst_ops,
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.of_reset_n_cells = 1,
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};
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void tegra_clk_init_rst_controller(void __iomem *base, struct device_node *np,
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unsigned int num)
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{
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car_base = base;
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rst_ctlr.of_node = np;
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rst_ctlr.nr_resets = num;
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reset_controller_register(&rst_ctlr);
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}
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void tegra_clk_reset_uarts(void) {
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int i;
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int console_device_ids[] = {6, 7, 55, 65, 66};
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for (i = 0; i < ARRAY_SIZE(console_device_ids); i++) {
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rst_ops.assert(&rst_ctlr, console_device_ids[i]);
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udelay(2);
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rst_ops.deassert(&rst_ctlr, console_device_ids[i]);
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}
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};
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