360 lines
11 KiB
C
360 lines
11 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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#ifndef INCLUDED_NVBOOT_BCT_T124_H
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#define INCLUDED_NVBOOT_BCT_T124_H
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#include <sys/types.h>
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#include "nvboot_sdram_param_t124.h"
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/**
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* Defines the number of 32-bit words in the customer_data area of the BCT.
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*/
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#define NVBOOT_BCT_CUSTOMER_DATA_WORDS 162
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/**
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* Defines the number of bytes in the customer_data area of the BCT.
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*/
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#define NVBOOT_BCT_CUSTOMER_DATA_SIZE \
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(NVBOOT_BCT_CUSTOMER_DATA_WORDS * 4)
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/**
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* Defines the number of bytes in the reserved area of the BCT.
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*/
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#define NVBOOT_BCT_RESERVED_SIZE 2
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/**
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* Defines the maximum number of bootloader descriptions in the BCT.
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*/
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#define NVBOOT_MAX_BOOTLOADERS 4
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/**
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* Defines the maximum number of device parameter sets in the BCT.
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* The value must be equal to (1 << # of device straps)
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*/
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#define NVBOOT_BCT_MAX_PARAM_SETS 4
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/**
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* Defines the maximum number of SDRAM parameter sets in the BCT.
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* The value must be equal to (1 << # of SDRAM straps)
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*/
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#define NVBOOT_BCT_MAX_SDRAM_SETS 4
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/**
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* Defines the number of entries (bits) in the bad block table.
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* The consequences of changing its value are as follows. Using P as the
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* # of physical blocks in the boot loader and B as the value of this
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* constant:
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* B > P: There will be unused storage in the bad block table.
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* B < P: The virtual block size will be greater than the physical block
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* size, so the granularity of the bad block table will be less than
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* one bit per physical block.
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*
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* 4096 bits is enough to represent an 8MiB partition of 2KiB blocks with one
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* bit per block (1 virtual block = 1 physical block). This occupies 512 bytes
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* of storage.
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*/
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#define NVBOOT_BAD_BLOCK_TABLE_SIZE 4096
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/**
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* Defines the amount of padding needed to pad the bad block table to a
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* multiple of AES block size.
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*/
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#define NVBOOT_BAD_BLOCK_TABLE_PADDING 10
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/**
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* Defines the maximum number of blocks to search for BCTs.
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*
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* This value covers the initial block and a set of journal blocks.
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*
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* Ideally, this number will span several erase units for reliable updates
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* and tolerance for blocks to become bad with use. Safe updates require
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* a minimum of 2 erase units in which BCTs can appear.
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*
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* To ensure that the BCT search spans a sufficient range of configurations,
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* the search block count has been set to 64. This allows for redundancy with
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* a wide range of parts and provides room for greater problems in this
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* region of the device.
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*/
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#define NVBOOT_MAX_BCT_SEARCH_BLOCKS 64
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#define ARSE_RSA_MAX_MODULUS_SIZE 2048
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/**
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* Defines the RSA modulus length in bits and bytes used for PKC secure boot.
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*/
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enum {NVBOOT_SE_RSA_MODULUS_LENGTH_BITS = ARSE_RSA_MAX_MODULUS_SIZE};
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/*
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* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words)
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*/
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enum {NVBOOT_CMAC_AES_HASH_LENGTH = 4};
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/**
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* Defines the storage for a hash value (128 bits).
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*/
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typedef struct nvboot_hash_rec {
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u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH];
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} nvboot_hash;
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/*
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* Defines the storage for the RSA public key's modulus
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* in the BCT
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*/
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typedef struct nvboot_rsa_key_modulus_rec {
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/* The modulus size is 2048-bits. */
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u_int32_t modulus[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4];
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} nvboot_rsa_key_modulus;
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typedef struct nvboot_rsa_pss_sig_rec {
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/*
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* The RSA-PSS signature length is equal to the
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* length in octets of the RSA modulus.
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* In our case, it's 2048-bits.
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*/
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u_int32_t signature[NVBOOT_SE_RSA_MODULUS_LENGTH_BITS / 8 / 4];
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} nvboot_rsa_pss_sig;
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typedef struct nvboot_object_signature_rec {
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/*
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* Specifies the AES-CMAC signature for the rest of the BCT structure if symmetric key
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* encryption secure boot scheme is used.
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*/
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nvboot_hash crypto_hash;
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/*
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* Specifies the RSASSA-PSS signature for the rest of the BCT structure if public
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* key cryptography secure boot scheme is used.
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*/
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nvboot_rsa_pss_sig rsa_pss_sig;
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} nvboot_object_signature;
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typedef struct nvboot_ecid_rec {
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u_int32_t ecid_0;
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u_int32_t ecid_1;
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u_int32_t ecid_2;
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u_int32_t ecid_3;
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} nvboot_ecid;
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/* Defines various data widths supported. */
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typedef enum {
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/**
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* Specifies a 1 bit interface to eMMC.
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* Note that 1-bit data width is only for the driver's internal use.
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* Fuses doesn't provide option to select 1-bit data width.
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* The driver selects 1-bit internally based on need.
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* It is used for reading Extended CSD and when the power class
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* requirements of a card for 4-bit or 8-bit transfers are not
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* supported by the target board.
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*/
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nvboot_sdmmc_data_width_1bit = 0,
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/* Specifies a 4 bit interface to eMMC. */
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nvboot_sdmmc_data_width_4bit = 1,
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/* Specifies a 8 bit interface to eMMC. */
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nvboot_sdmmc_data_width_8bit = 2,
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/* Specifies a 4 bit Ddr interface to eMMC. */
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nvboot_sdmmc_data_width_ddr_4bit = 5,
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/* Specifies a 8 bit Ddr interface to eMMC. */
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nvboot_sdmmc_data_width_ddr_8bit = 6,
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nvboot_sdmmc_data_width_num,
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nvboot_sdmmc_data_width_force32 = 0x7FFFFFFF
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} nvboot_sdmmc_data_width;
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/* Defines the parameters that can be changed after BCT is read. */
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typedef struct nvboot_sdmmc_params_rec {
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/**
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* Specifies the clock divider for the SDMMC controller's clock source,
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* which is PLLP running at 216MHz. If it is set to 9, then the SDMMC
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* controller runs at 216/9 = 24MHz.
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*/
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u_int8_t clock_divider;
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/* Specifies the data bus width. Supported data widths are 4/8 bits. */
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nvboot_sdmmc_data_width data_width;
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/**
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* Max Power class supported by the target board.
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* The driver determines the best data width and clock frequency
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* supported within the power class range (0 to Max) if the selected
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* data width cannot be used at the chosen clock frequency.
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*/
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u_int8_t max_power_class_supported;
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/* Specifies the max page size supported by driver */
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u_int8_t multi_page_support;
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} nvboot_sdmmc_params;
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typedef enum {
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/* Specifies SPI clock source to be PLLP. */
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nvboot_spi_clock_source_pllp_out0 = 0,
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/* Specifies SPI clock source to be ClockM. */
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nvboot_spi_clock_source_clockm = 6,
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nvboot_spi_clock_source_num,
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nvboot_spi_clock_source_force32 = 0x7FFFFFF
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} nvboot_spi_clock_source;
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/**
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* Defines the parameters SPI FLASH devices.
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*/
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typedef struct nvboot_spiflash_params_rec {
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/**
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* Specifies the clock source to use.
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*/
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u_int32_t clock_source;
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/**
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* Specifes the clock divider to use.
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* The value is a 7-bit value based on an input clock of 432Mhz.
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* Divider = (432+ DesiredFrequency-1)/DesiredFrequency;
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* Typical values:
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* NORMAL_READ at 20MHz: 22
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* FAST_READ at 33MHz: 14
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* FAST_READ at 40MHz: 11
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* FAST_READ at 50MHz: 9
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*/
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u_int8_t clock_divider;
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/**
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* Specifies the type of command for read operations.
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* NV_FALSE specifies a NORMAL_READ Command
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* NV_TRUE specifies a FAST_READ Command
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*/
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u_int8_t read_command_type_fast;
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/* 0 = 2k page size, 1 = 16K page size */
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u_int8_t page_size_2k_or_16k;
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} nvboot_spiflash_params;
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/**
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* Defines the union of the parameters required by each device.
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*/
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typedef union {
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u_int8_t size[64];
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/* Specifies optimized parameters for eMMC and eSD */
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nvboot_sdmmc_params sdmmc_params;
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/* Specifies optimized parameters for SPI NOR */
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nvboot_spiflash_params spiflash_params;
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} nvboot_dev_params;
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/**
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* Identifies the types of devices from which the system booted.
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* Used to identify primary and secondary boot devices.
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* @note These no longer match the fuse API device values (for
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* backward compatibility with AP15).
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*/
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typedef enum {
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/* Specifies a default (unset) value. */
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nvboot_dev_type_none = 0,
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/* Specifies SPI NOR. */
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nvboot_dev_type_spi = 3,
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/* Specifies SDMMC (either eMMC or eSD). */
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nvboot_dev_type_sdmmc = 4,
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nvboot_dev_type_max,
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/* Ignore -- Forces compilers to make 32-bit enums. */
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nvboot_dev_type_force32 = 0x7FFFFFFF
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} nvboot_dev_type;
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/**
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* Stores information needed to locate and verify a boot loader.
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*
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* There is one \c nv_bootloader_info structure for each copy of a BL stored on
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* the device.
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*/
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typedef struct nv_bootloader_info_rec {
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u_int32_t version;
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u_int32_t start_blk;
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u_int32_t start_page;
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u_int32_t length;
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u_int32_t load_addr;
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u_int32_t entry_point;
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u_int32_t attribute;
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/* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */
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nvboot_object_signature signature;
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} nv_bootloader_info;
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/**
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* Defines the bad block table structure stored in the BCT.
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*/
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typedef struct nvboot_badblock_table_rec {
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u_int32_t entries_used;
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u_int8_t virtual_blk_size_log2;
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u_int8_t block_size_log2;
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u_int8_t bad_blks[NVBOOT_BAD_BLOCK_TABLE_SIZE / 8];
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/*
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* Add a reserved field as padding to make the bad block table structure
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* a multiple of 16 bytes (AES block size).
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*/
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u_int8_t reserved[NVBOOT_BAD_BLOCK_TABLE_PADDING];
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} nvboot_badblock_table;
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/**
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* Contains the information needed to load BLs from the secondary boot device.
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*
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* - Supplying NumParamSets = 0 indicates not to load any of them.
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* - Supplying NumDramSets = 0 indicates not to load any of them.
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* - The \c random_aes_blk member exists to increase the difficulty of
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* key attacks based on knowledge of this structure.
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*/
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typedef struct nvboot_config_table_rec {
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nvboot_badblock_table badblock_table;
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nvboot_rsa_key_modulus key;
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nvboot_object_signature signature;
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u_int8_t customer_data[NVBOOT_BCT_CUSTOMER_DATA_SIZE];
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u_int32_t odm_data;
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u_int32_t reserved1;
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/* START OF SIGNED SECTION OF THE BCT */
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nvboot_hash random_aes_blk;
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nvboot_ecid unique_chip_id;
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u_int32_t boot_data_version;
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u_int32_t block_size_log2;
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u_int32_t page_size_log2;
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u_int32_t partition_size;
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u_int32_t num_param_sets;
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nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS];
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nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS];
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u_int32_t num_sdram_sets;
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nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS];
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u_int32_t bootloader_used;
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nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
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u_int8_t enable_fail_back;
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/*
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* Specify whether or not to enable JTAG access when the JTAG disable fuse
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* has not been burned.
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* SecureJtagControl = NV_FALSE (0) = Disable JTAG access.
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* SecureJtagControl = NV_TRUE (1) = Enable JTAG access.
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*/
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u_int8_t secure_jtag_control;
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u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE];
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} nvboot_config_table;
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#endif /* #ifndef INCLUDED_NVBOOT_BCT_T124_H */
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