430 lines
22 KiB
C
430 lines
22 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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/*
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* parse_t124.c - The implementation for parsing dev/sdram parameters
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*/
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#include "../parse.h"
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#include "nvboot_bct_t124.h"
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enum_item s_devtype_table_t124[] = {
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{ "NvBootDevType_Sdmmc", nvboot_dev_type_sdmmc },
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{ "NvBootDevType_Spi", nvboot_dev_type_spi },
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{ "Sdmmc", nvboot_dev_type_sdmmc },
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{ "Spi", nvboot_dev_type_spi },
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{ NULL, 0 }
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};
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enum_item s_sdmmc_data_width_table_t124[] = {
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{
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"NvBootSdmmcDataWidth_4Bit",
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nvboot_sdmmc_data_width_4bit
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},
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{
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"NvBootSdmmcDataWidth_8Bit",
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nvboot_sdmmc_data_width_8bit
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},
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{ "4Bit", nvboot_sdmmc_data_width_4bit },
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{ "8Bit", nvboot_sdmmc_data_width_8bit },
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{ NULL, 0 }
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};
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enum_item s_spi_clock_source_table_t124[] = {
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{ "NvBootSpiClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 },
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{ "NvBootSpiClockSource_ClockM", nvboot_spi_clock_source_clockm },
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{ "ClockSource_PllPOut0", nvboot_spi_clock_source_pllp_out0 },
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{ "ClockSource_ClockM", nvboot_spi_clock_source_clockm },
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{ "PllPOut0", nvboot_spi_clock_source_pllp_out0 },
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{ "ClockM", nvboot_spi_clock_source_clockm },
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{ NULL, 0 }
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};
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enum_item s_nvboot_memory_type_table_t124[] = {
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{ "NvBootMemoryType_None", nvboot_memory_type_none },
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{ "NvBootMemoryType_Ddr3", nvboot_memory_type_ddr3 },
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{ "NvBootMemoryType_Ddr2", nvboot_memory_type_ddr2 },
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{ "NvBootMemoryType_Ddr", nvboot_memory_type_ddr },
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{ "NvBootMemoryType_LpDdr2", nvboot_memory_type_lpddr2 },
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{ "NvBootMemoryType_LpDdr", nvboot_memory_type_lpddr },
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{ "None", nvboot_memory_type_none },
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{ "Ddr3", nvboot_memory_type_ddr3 },
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{ "Ddr2", nvboot_memory_type_ddr2 },
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{ "Ddr", nvboot_memory_type_ddr },
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{ "LpDdr2", nvboot_memory_type_lpddr2 },
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{ "LpDdr", nvboot_memory_type_lpddr },
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{ NULL, 0 }
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};
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#define TOKEN(name) \
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token_##name, field_type_u32, NULL
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field_item s_sdram_field_table_t124[] = {
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{ "MemoryType", token_memory_type,
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field_type_enum, s_nvboot_memory_type_table_t124 },
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{ "PllMInputDivider", TOKEN(pllm_input_divider) },
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{ "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) },
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{ "PllMStableTime", TOKEN(pllm_stable_time) },
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{ "PllMSetupControl", TOKEN(pllm_setup_control) },
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{ "PllMSelectDiv2", TOKEN(pllm_select_div2) },
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{ "PllMPDLshiftPh45", TOKEN(pllm_pdlshift_ph45) },
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{ "PllMPDLshiftPh90", TOKEN(pllm_pdlshift_ph90) },
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{ "PllMPDLshiftPh135", TOKEN(pllm_pdlshift_ph135) },
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{ "PllMKCP", TOKEN(pllm_kcp) },
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{ "PllMKVCO", TOKEN(pllm_kvco) },
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{ "EmcBctSpare0", TOKEN(emc_bct_spare0) },
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{ "EmcBctSpare1", TOKEN(emc_bct_spare1) },
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{ "EmcBctSpare2", TOKEN(emc_bct_spare2) },
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{ "EmcBctSpare3", TOKEN(emc_bct_spare3) },
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{ "EmcBctSpare4", TOKEN(emc_bct_spare4) },
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{ "EmcBctSpare5", TOKEN(emc_bct_spare5) },
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{ "EmcBctSpare6", TOKEN(emc_bct_spare6) },
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{ "EmcBctSpare7", TOKEN(emc_bct_spare7) },
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{ "EmcBctSpare8", TOKEN(emc_bct_spare8) },
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{ "EmcBctSpare9", TOKEN(emc_bct_spare9) },
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{ "EmcBctSpare10", TOKEN(emc_bct_spare10) },
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{ "EmcBctSpare11", TOKEN(emc_bct_spare11) },
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{ "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) },
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{ "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) },
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{ "EmcAutoCalConfig2", TOKEN(emc_auto_cal_config2) },
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{ "EmcAutoCalConfig3", TOKEN(emc_auto_cal_config3) },
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{ "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) },
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{ "EmcPinProgramWait", TOKEN(emc_pin_program_wait) },
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{ "EmcRc", TOKEN(emc_rc) },
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{ "EmcRfc", TOKEN(emc_rfc) },
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{ "EmcRfcSlr", TOKEN(emc_rfc_slr) },
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{ "EmcRas", TOKEN(emc_ras) },
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{ "EmcRp", TOKEN(emc_rp) },
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{ "EmcR2r", TOKEN(emc_r2r) },
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{ "EmcW2w", TOKEN(emc_w2w) },
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{ "EmcR2w", TOKEN(emc_r2w) },
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{ "EmcW2r", TOKEN(emc_w2r) },
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{ "EmcR2p", TOKEN(emc_r2p) },
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{ "EmcW2p", TOKEN(emc_w2p) },
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{ "EmcRrd", TOKEN(emc_rrd) },
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{ "EmcRdRcd", TOKEN(emc_rd_rcd) },
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{ "EmcWrRcd", TOKEN(emc_wr_rcd) },
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{ "EmcRext", TOKEN(emc_rext) },
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{ "EmcWdv", TOKEN(emc_wdv) },
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{ "EmcWdvMask", TOKEN(emc_wdv_mask) },
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{ "EmcQUse", TOKEN(emc_quse) },
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{ "EmcQuseWidth", TOKEN(emc_quse_width) },
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{ "EmcIbdly", TOKEN(emc_ibdly) },
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{ "EmcEInput", TOKEN(emc_einput) },
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{ "EmcEInputDuration", TOKEN(emc_einput_duration) },
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{ "EmcPutermExtra", TOKEN(emc_puterm_extra) },
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{ "EmcPutermWidth", TOKEN(emc_puterm_width) },
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{ "EmcPutermAdj", TOKEN(emc_puterm_adj) },
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{ "EmcCdbCntl1", TOKEN(emc_cdb_cntl1) },
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{ "EmcCdbCntl2", TOKEN(emc_cdb_cntl2) },
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{ "EmcCdbCntl3", TOKEN(emc_cdb_cntl3) },
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{ "EmcQRst", TOKEN(emc_qrst) },
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{ "EmcQSafe", TOKEN(emc_qsafe) },
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{ "EmcRdv", TOKEN(emc_rdv) },
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{ "EmcRdvMask", TOKEN(emc_rdv_mask) },
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{ "EmcQpop", TOKEN(emc_qpop) },
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{ "EmcRefresh", TOKEN(emc_refresh) },
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{ "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) },
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{ "EmcPdEx2Wr", TOKEN(emc_pdex2wr) },
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{ "EmcPdEx2Rd", TOKEN(emc_pdex2rd) },
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{ "EmcPChg2Pden", TOKEN(emc_pchg2pden) },
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{ "EmcAct2Pden", TOKEN(emc_act2pden) },
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{ "EmcAr2Pden", TOKEN(emc_ar2pden) },
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{ "EmcRw2Pden", TOKEN(emc_rw2pden) },
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{ "EmcTxsr", TOKEN(emc_txsr) },
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{ "EmcTcke", TOKEN(emc_tcke) },
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{ "EmcTckesr", TOKEN(emc_tckesr) },
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{ "EmcTpd", TOKEN(emc_tpd) },
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{ "EmcTfaw", TOKEN(emc_tfaw) },
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{ "EmcTrpab", TOKEN(emc_trpab) },
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{ "EmcTClkStable", TOKEN(emc_tclkstable) },
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{ "EmcTClkStop", TOKEN(emc_tclkstop) },
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{ "EmcTRefBw", TOKEN(emc_trefbw) },
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{ "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) },
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{ "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) },
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{ "EmcFbioSpare", TOKEN(emc_fbio_spare) },
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{ "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) },
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{ "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) },
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{ "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) },
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{ "EmcMrs", TOKEN(emc_mrs) },
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{ "EmcEmrs2", TOKEN(emc_emrs2) },
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{ "EmcEmrs3", TOKEN(emc_emrs3) },
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{ "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) },
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{ "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) },
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{ "EmcEmrs", TOKEN(emc_emrs) },
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{ "EmcMrw1", TOKEN(emc_mrw1) },
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{ "EmcMrw2", TOKEN(emc_mrw2) },
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{ "EmcMrw3", TOKEN(emc_mrw3) },
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{ "EmcMrw4", TOKEN(emc_mrw4) },
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{ "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) },
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{ "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) },
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{ "EmcAdrCfg", TOKEN(emc_adr_cfg) },
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{ "McEmemCfg", TOKEN(mc_emem_cfg) },
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{ "EmcCfg2", TOKEN(emc_cfg2) },
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{ "EmcCfgPipe", TOKEN(emc_cfg_pipe) },
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{ "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) },
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{ "EmcCfgDigDllPeriod", TOKEN(emc_cfg_dig_dll_period) },
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{ "EmcCfg", TOKEN(emc_cfg) },
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{ "EmcDbg", TOKEN(emc_dbg) },
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{ "WarmBootWait", TOKEN(warm_boot_wait) },
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{ "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) },
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{ "EmcOdtWrite", TOKEN(emc_odt_write) },
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{ "EmcOdtRead", TOKEN(emc_odt_read) },
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{ "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) },
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{ "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) },
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{ "EmcDdr2Wait", TOKEN(emc_ddr2_wait) },
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{ "PmcDdrPwr", TOKEN(pmc_ddr_pwr) },
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{ "EmcClockSource", TOKEN(emc_clock_source) },
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{ "EmcPinExtraWait", TOKEN(emc_pin_extra_wait) },
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{ "EmcTimingControlWait", TOKEN(emc_timing_control_wait) },
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{ "EmcWext", TOKEN(emc_wext) },
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{ "EmcCtt", TOKEN(emc_ctt) },
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{ "EmcCttDuration", TOKEN(emc_ctt_duration) },
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{ "EmcPreRefreshReqCnt", TOKEN(emc_prerefresh_req_cnt) },
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{ "EmcTxsrDll", TOKEN(emc_txsr_dll) },
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{ "EmcCfgRsv", TOKEN(emc_cfg_rsv) },
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{ "EmcMrwExtra", TOKEN(emc_mrw_extra) },
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{ "EmcWarmBootMrwExtra", TOKEN(emc_warm_boot_mrw_extra) },
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{ "EmcWarmBootExtraModeRegWriteEnable",
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TOKEN(emc_warm_boot_extramode_reg_write_enable) },
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{ "EmcExtraModeRegWriteEnable", TOKEN(emc_extramode_reg_write_enable) },
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{ "EmcMrsWaitCnt", TOKEN(emc_mrs_wait_cnt) },
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{ "EmcMrsWaitCnt2", TOKEN(emc_mrs_wait_cnt2) },
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{ "EmcCmdQ", TOKEN(emc_cmd_q) },
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{ "EmcMc2EmcQ", TOKEN(emc_mc2emc_q) },
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{ "EmcDynSelfRefControl", TOKEN(emc_dyn_self_ref_control) },
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{ "AhbArbitrationXbarCtrlMemInitDone",
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TOKEN(ahb_arbitration_xbar_ctrl_meminit_done) },
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{ "EmcDevSelect", TOKEN(emc_dev_select) },
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{ "EmcSelDpdCtrl", TOKEN(emc_sel_dpd_ctrl) },
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{ "EmcDllXformDqs0", TOKEN(emc_dll_xform_dqs0) },
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{ "EmcDllXformDqs1", TOKEN(emc_dll_xform_dqs1) },
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{ "EmcDllXformDqs2", TOKEN(emc_dll_xform_dqs2) },
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{ "EmcDllXformDqs3", TOKEN(emc_dll_xform_dqs3) },
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{ "EmcDllXformDqs4", TOKEN(emc_dll_xform_dqs4) },
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{ "EmcDllXformDqs5", TOKEN(emc_dll_xform_dqs5) },
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{ "EmcDllXformDqs6", TOKEN(emc_dll_xform_dqs6) },
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{ "EmcDllXformDqs7", TOKEN(emc_dll_xform_dqs7) },
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{ "EmcDllXformDqs8", TOKEN(emc_dll_xform_dqs8) },
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{ "EmcDllXformDqs9", TOKEN(emc_dll_xform_dqs9) },
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{ "EmcDllXformDqs10", TOKEN(emc_dll_xform_dqs10) },
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{ "EmcDllXformDqs11", TOKEN(emc_dll_xform_dqs11) },
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{ "EmcDllXformDqs12", TOKEN(emc_dll_xform_dqs12) },
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{ "EmcDllXformDqs13", TOKEN(emc_dll_xform_dqs13) },
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{ "EmcDllXformDqs14", TOKEN(emc_dll_xform_dqs14) },
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{ "EmcDllXformDqs15", TOKEN(emc_dll_xform_dqs15) },
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{ "EmcDllXformQUse0", TOKEN(emc_dll_xform_quse0) },
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{ "EmcDllXformQUse1", TOKEN(emc_dll_xform_quse1) },
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{ "EmcDllXformQUse2", TOKEN(emc_dll_xform_quse2) },
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{ "EmcDllXformQUse3", TOKEN(emc_dll_xform_quse3) },
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{ "EmcDllXformQUse4", TOKEN(emc_dll_xform_quse4) },
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{ "EmcDllXformQUse5", TOKEN(emc_dll_xform_quse5) },
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{ "EmcDllXformQUse6", TOKEN(emc_dll_xform_quse6) },
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{ "EmcDllXformQUse7", TOKEN(emc_dll_xform_quse7) },
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{ "EmcDllXformAddr0", TOKEN(emc_dll_xform_addr0) },
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{ "EmcDllXformAddr1", TOKEN(emc_dll_xform_addr1) },
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{ "EmcDllXformAddr2", TOKEN(emc_dll_xform_addr2) },
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{ "EmcDllXformAddr3", TOKEN(emc_dll_xform_addr3) },
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{ "EmcDllXformAddr4", TOKEN(emc_dll_xform_addr4) },
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{ "EmcDllXformAddr5", TOKEN(emc_dll_xform_addr5) },
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{ "EmcDllXformQUse8", TOKEN(emc_dll_xform_quse8) },
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{ "EmcDllXformQUse9", TOKEN(emc_dll_xform_quse9) },
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{ "EmcDllXformQUse10", TOKEN(emc_dll_xform_quse10) },
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{ "EmcDllXformQUse11", TOKEN(emc_dll_xform_quse11) },
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{ "EmcDllXformQUse12", TOKEN(emc_dll_xform_quse12) },
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{ "EmcDllXformQUse13", TOKEN(emc_dll_xform_quse13) },
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{ "EmcDllXformQUse14", TOKEN(emc_dll_xform_quse14) },
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{ "EmcDllXformQUse15", TOKEN(emc_dll_xform_quse15) },
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{ "EmcDliTrimTxDqs0", TOKEN(emc_dli_trim_tx_dqs0) },
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{ "EmcDliTrimTxDqs1", TOKEN(emc_dli_trim_tx_dqs1) },
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{ "EmcDliTrimTxDqs2", TOKEN(emc_dli_trim_tx_dqs2) },
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{ "EmcDliTrimTxDqs3", TOKEN(emc_dli_trim_tx_dqs3) },
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{ "EmcDliTrimTxDqs4", TOKEN(emc_dli_trim_tx_dqs4) },
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{ "EmcDliTrimTxDqs5", TOKEN(emc_dli_trim_tx_dqs5) },
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{ "EmcDliTrimTxDqs6", TOKEN(emc_dli_trim_tx_dqs6) },
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{ "EmcDliTrimTxDqs7", TOKEN(emc_dli_trim_tx_dqs7) },
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{ "EmcDliTrimTxDqs8", TOKEN(emc_dli_trim_tx_dqs8) },
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{ "EmcDliTrimTxDqs9", TOKEN(emc_dli_trim_tx_dqs9) },
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{ "EmcDliTrimTxDqs10", TOKEN(emc_dli_trim_tx_dqs10) },
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{ "EmcDliTrimTxDqs11", TOKEN(emc_dli_trim_tx_dqs11) },
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{ "EmcDliTrimTxDqs12", TOKEN(emc_dli_trim_tx_dqs12) },
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{ "EmcDliTrimTxDqs13", TOKEN(emc_dli_trim_tx_dqs13) },
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{ "EmcDliTrimTxDqs14", TOKEN(emc_dli_trim_tx_dqs14) },
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{ "EmcDliTrimTxDqs15", TOKEN(emc_dli_trim_tx_dqs15) },
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{ "EmcDllXformDq0", TOKEN(emc_dll_xform_dq0) },
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{ "EmcDllXformDq1", TOKEN(emc_dll_xform_dq1) },
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{ "EmcDllXformDq2", TOKEN(emc_dll_xform_dq2) },
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{ "EmcDllXformDq3", TOKEN(emc_dll_xform_dq3) },
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{ "EmcDllXformDq4", TOKEN(emc_dll_xform_dq4) },
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{ "EmcDllXformDq5", TOKEN(emc_dll_xform_dq5) },
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{ "EmcDllXformDq6", TOKEN(emc_dll_xform_dq6) },
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{ "EmcDllXformDq7", TOKEN(emc_dll_xform_dq7) },
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{ "EmcZcalInterval", TOKEN(emc_zcal_interval) },
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{ "EmcZcalInitDev0", TOKEN(emc_zcal_init_dev0) },
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{ "EmcZcalInitDev1", TOKEN(emc_zcal_init_dev1) },
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{ "EmcZcalInitWait", TOKEN(emc_zcal_init_wait) },
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{ "EmcZcalWarmColdBootEnables", TOKEN(emc_zcal_warm_cold_boot_enables) },
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{ "EmcMrwLpddr2ZcalWarmBoot", TOKEN(emc_mrw_lpddr2zcal_warm_boot) },
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{ "EmcZqCalDdr3WarmBoot", TOKEN(emc_zqcal_ddr3_warm_boot) },
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{ "EmcZcalWarmBootWait", TOKEN(emc_zcal_warm_boot_wait) },
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{ "EmcMrsWarmBootEnable", TOKEN(emc_mrs_warm_boot_enable) },
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{ "EmcMrsExtra", TOKEN(emc_mrs_extra) },
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{ "EmcWarmBootMrsExtra", TOKEN(emc_warm_boot_mrs_extra) },
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{ "EmcClkenOverride", TOKEN(emc_clken_override) },
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{ "McDisExtraSnapLevels", TOKEN(mc_dis_extra_snap_levels) },
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{ "EmcExtraRefreshNum", TOKEN(emc_extra_refresh_num) },
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{ "EmcClkenOverrideAllWarmBoot",
|
|
TOKEN(emc_clken_override_allwarm_boot) },
|
|
{ "McClkenOverrideAllWarmBoot", TOKEN(mc_clken_override_allwarm_boot) },
|
|
{ "EmcCfgDigDllPeriodWarmBoot",
|
|
TOKEN(emc_cfg_dig_dll_period_warm_boot) },
|
|
{ "PmcVddpSel", TOKEN(pmc_vddp_sel) },
|
|
{ "PmcVddpSelWait", TOKEN(pmc_vddp_sel_wait) },
|
|
{ "PmcDdrCfg", TOKEN(pmc_ddr_cfg) },
|
|
{ "PmcIoDpd3Req", TOKEN(pmc_io_dpd3_req) },
|
|
{ "PmcIoDpd3ReqWait", TOKEN(pmc_io_dpd3_req_wait) },
|
|
{ "PmcRegShort", TOKEN(pmc_reg_short) },
|
|
{ "PmcNoIoPower", TOKEN(pmc_no_io_power) },
|
|
{ "PmcPorDpdCtrlWait", TOKEN(pmc_por_dpd_ctrl_wait) },
|
|
{ "EmcXm2CmdPadCtrl", TOKEN(emc_xm2cmd_pad_ctrl) },
|
|
{ "EmcXm2CmdPadCtrl2", TOKEN(emc_xm2cmd_pad_ctrl2) },
|
|
{ "EmcXm2CmdPadCtrl3", TOKEN(emc_xm2cmd_pad_ctrl3) },
|
|
{ "EmcXm2CmdPadCtrl4", TOKEN(emc_xm2cmd_pad_ctrl4) },
|
|
{ "EmcXm2CmdPadCtrl5", TOKEN(emc_xm2cmd_pad_ctrl5) },
|
|
{ "EmcXm2DqsPadCtrl", TOKEN(emc_xm2dqs_pad_ctrl) },
|
|
{ "EmcXm2DqsPadCtrl2", TOKEN(emc_xm2dqs_pad_ctrl2) },
|
|
{ "EmcXm2DqsPadCtrl3", TOKEN(emc_xm2dqs_pad_ctrl3) },
|
|
{ "EmcXm2DqsPadCtrl4", TOKEN(emc_xm2dqs_pad_ctrl4) },
|
|
{ "EmcXm2DqsPadCtrl5", TOKEN(emc_xm2dqs_pad_ctrl5) },
|
|
{ "EmcXm2DqsPadCtrl6", TOKEN(emc_xm2dqs_pad_ctrl6) },
|
|
{ "EmcXm2DqPadCtrl", TOKEN(emc_xm2dq_pad_ctrl) },
|
|
{ "EmcXm2DqPadCtrl2", TOKEN(emc_xm2dq_pad_ctrl2) },
|
|
{ "EmcXm2DqPadCtrl3", TOKEN(emc_xm2dq_pad_ctrl3) },
|
|
{ "EmcXm2ClkPadCtrl", TOKEN(emc_xm2clk_pad_ctrl) },
|
|
{ "EmcXm2ClkPadCtrl2", TOKEN(emc_xm2clk_pad_ctrl2) },
|
|
{ "EmcXm2CompPadCtrl", TOKEN(emc_xm2comp_pad_ctrl) },
|
|
{ "EmcXm2VttGenPadCtrl", TOKEN(emc_xm2vttgen_pad_ctrl) },
|
|
{ "EmcXm2VttGenPadCtrl2", TOKEN(emc_xm2vttgen_pad_ctrl2) },
|
|
{ "EmcXm2VttGenPadCtrl3", TOKEN(emc_xm2vttgen_pad_ctrl3) },
|
|
{ "EmcAcpdControl", TOKEN(emc_acpd_control) },
|
|
{ "EmcSwizzleRank0ByteCfg", TOKEN(emc_swizzle_rank0_byte_cfg) },
|
|
{ "EmcSwizzleRank0Byte0", TOKEN(emc_swizzle_rank0_byte0) },
|
|
{ "EmcSwizzleRank0Byte1", TOKEN(emc_swizzle_rank0_byte1) },
|
|
{ "EmcSwizzleRank0Byte2", TOKEN(emc_swizzle_rank0_byte2) },
|
|
{ "EmcSwizzleRank0Byte3", TOKEN(emc_swizzle_rank0_byte3) },
|
|
{ "EmcSwizzleRank1ByteCfg", TOKEN(emc_swizzle_rank1_byte_cfg) },
|
|
{ "EmcSwizzleRank1Byte0", TOKEN(emc_swizzle_rank1_byte0) },
|
|
{ "EmcSwizzleRank1Byte1", TOKEN(emc_swizzle_rank1_byte1) },
|
|
{ "EmcSwizzleRank1Byte2", TOKEN(emc_swizzle_rank1_byte2) },
|
|
{ "EmcSwizzleRank1Byte3", TOKEN(emc_swizzle_rank1_byte3) },
|
|
{ "EmcDsrVttgenDrv", TOKEN(emc_dsr_vttgen_drv) },
|
|
{ "EmcTxdsrvttgen", TOKEN(emc_txdsrvttgen) },
|
|
{ "EmcBgbiasCtl0", TOKEN(emc_bgbias_ctl0) },
|
|
{ "McEmemAdrCfg", TOKEN(mc_emem_adr_cfg) },
|
|
{ "McEmemAdrCfgDev0", TOKEN(mc_emem_adr_cfg_dev0) },
|
|
{ "McEmemAdrCfgDev1", TOKEN(mc_emem_adr_cfg_dev1) },
|
|
{ "McEmemAdrCfgBankMask0", TOKEN(mc_emem_adr_cfg_bank_mask0) },
|
|
{ "McEmemAdrCfgBankMask1", TOKEN(mc_emem_adr_cfg_bank_mask1) },
|
|
{ "McEmemAdrCfgBankMask2", TOKEN(mc_emem_adr_cfg_bank_mask2) },
|
|
{ "McEmemAdrCfgBankSwizzle3", TOKEN(mc_emem_adr_cfg_bank_swizzle3) },
|
|
{ "McEmemArbCfg", TOKEN(mc_emem_arb_cfg) },
|
|
{ "McEmemArbOutstandingReq", TOKEN(mc_emem_arb_outstanding_req) },
|
|
{ "McEmemArbTimingRcd", TOKEN(mc_emem_arb_timing_rcd) },
|
|
{ "McEmemArbTimingRp", TOKEN(mc_emem_arb_timing_rp) },
|
|
{ "McEmemArbTimingRc", TOKEN(mc_emem_arb_timing_rc) },
|
|
{ "McEmemArbTimingRas", TOKEN(mc_emem_arb_timing_ras) },
|
|
{ "McEmemArbTimingFaw", TOKEN(mc_emem_arb_timing_faw) },
|
|
{ "McEmemArbTimingRrd", TOKEN(mc_emem_arb_timing_rrd) },
|
|
{ "McEmemArbTimingRap2Pre", TOKEN(mc_emem_arb_timing_rap2pre) },
|
|
{ "McEmemArbTimingWap2Pre", TOKEN(mc_emem_arb_timing_wap2pre) },
|
|
{ "McEmemArbTimingR2R", TOKEN(mc_emem_arb_timing_r2r) },
|
|
{ "McEmemArbTimingW2W", TOKEN(mc_emem_arb_timing_w2w) },
|
|
{ "McEmemArbTimingR2W", TOKEN(mc_emem_arb_timing_r2w) },
|
|
{ "McEmemArbTimingW2R", TOKEN(mc_emem_arb_timing_w2r) },
|
|
{ "McEmemArbDaTurns", TOKEN(mc_emem_arb_da_turns) },
|
|
{ "McEmemArbDaCovers", TOKEN(mc_emem_arb_da_covers) },
|
|
{ "McEmemArbMisc0", TOKEN(mc_emem_arb_misc0) },
|
|
{ "McEmemArbMisc1", TOKEN(mc_emem_arb_misc1) },
|
|
{ "McEmemArbRing1Throttle", TOKEN(mc_emem_arb_ring1_throttle) },
|
|
{ "McEmemArbOverride", TOKEN(mc_emem_arb_override) },
|
|
{ "McEmemArbOverride1", TOKEN(mc_emem_arb_override1) },
|
|
{ "McEmemArbRsv", TOKEN(mc_emem_arb_rsv) },
|
|
{ "McClkenOverride", TOKEN(mc_clken_override) },
|
|
{ "McStatControl", TOKEN(mc_stat_control) },
|
|
{ "McDisplaySnapRing", TOKEN(mc_display_snap_ring) },
|
|
{ "McVideoProtectBom", TOKEN(mc_video_protect_bom) },
|
|
{ "McVideoProtectBomAdrHi",
|
|
TOKEN(mc_video_protect_bom_adr_hi) },
|
|
{ "McVideoProtectSizeMb", TOKEN(mc_video_protect_size_mb) },
|
|
{ "McVideoProtectVprOverride", TOKEN(mc_video_protect_vpr_override) },
|
|
{ "McVideoProtectVprOverride1", TOKEN(mc_video_protect_vpr_override1) },
|
|
{ "McVideoProtectGpuOverride0", TOKEN(mc_video_protect_gpu_override0) },
|
|
{ "McVideoProtectGpuOverride1", TOKEN(mc_video_protect_gpu_override1) },
|
|
{ "McSecCarveoutBom", TOKEN(mc_sec_carveout_bom) },
|
|
{ "McSecCarveoutAdrHi", TOKEN(mc_sec_carveout_adr_hi) },
|
|
{ "McSecCarveoutSizeMb", TOKEN(mc_sec_carveout_size_mb) },
|
|
{ "McVideoProtectWriteAccess", TOKEN(mc_video_protect_write_access) },
|
|
{ "McSecCarveoutProtectWriteAccess",
|
|
TOKEN(mc_sec_carveout_protect_write_access) },
|
|
{ "EmcCaTrainingEnable", TOKEN(emc_ca_training_enable) },
|
|
{ "EmcCaTrainingTimingCntl1", TOKEN(emc_ca_training_timing_cntl1) },
|
|
{ "EmcCaTrainingTimingCntl2", TOKEN(emc_ca_training_timing_cntl2) },
|
|
{ "SwizzleRankByteEncode", TOKEN(swizzle_rank_byte_encode) },
|
|
{ "BootRomPatchControl", TOKEN(boot_rom_patch_control) },
|
|
{ "BootRomPatchData", TOKEN(boot_rom_patch_data) },
|
|
{ "McMtsCarveoutBom", TOKEN(mc_mts_carveout_bom) },
|
|
{ "McMtsCarveoutAdrHi", TOKEN(mc_mts_carveout_adr_hi) },
|
|
{ "McMtsCarveoutSizeMb", TOKEN(mc_mts_carveout_size_mb) },
|
|
{ "McMtsCarveoutRegCtrl", TOKEN(mc_mts_carveout_reg_ctrl) },
|
|
{ NULL, 0, 0, NULL }
|
|
};
|
|
|
|
field_item s_sdmmc_table_t124[] = {
|
|
{ "ClockDivider", TOKEN(sdmmc_clock_divider) },
|
|
{ "DataWidth",
|
|
token_sdmmc_data_width,
|
|
field_type_enum,
|
|
s_sdmmc_data_width_table_t124 },
|
|
{ "MaxPowerClassSupported", TOKEN(sdmmc_max_power_class_supported) },
|
|
{ "MultiPageSupport", TOKEN(sdmmc_multi_page_support) },
|
|
{ NULL, 0, 0, NULL }
|
|
};
|
|
|
|
field_item s_spiflash_table_t124[] = {
|
|
{ "ReadCommandTypeFast", TOKEN(spiflash_read_command_type_fast) },
|
|
{ "PageSize2kor16k", TOKEN(spiflash_page_size_2k_or_16k) },
|
|
{ "ClockDivider", TOKEN(spiflash_clock_divider) },
|
|
{ "ClockSource",
|
|
token_spiflash_clock_source,
|
|
field_type_enum,
|
|
s_spi_clock_source_table_t124 },
|
|
{ NULL, 0, 0, NULL }
|
|
};
|
|
|
|
parse_subfield_item s_device_type_table_t124[] = {
|
|
{ "SdmmcParams.", token_sdmmc_params,
|
|
s_sdmmc_table_t124, t124_set_dev_param },
|
|
{ "SpiFlashParams.", token_spiflash_params,
|
|
s_spiflash_table_t124, t124_set_dev_param },
|
|
{ NULL, 0, NULL }
|
|
};
|