685 lines
19 KiB
C
685 lines
19 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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#include "../cbootimage.h"
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#include "../parse.h"
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#include "../crypto.h"
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#include "nvboot_bct_t20.h"
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#include "string.h"
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/* nvbctlib_t20.c: The implementation of the nvbctlib API for t20. */
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/* Definitions that simplify the code which follows. */
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#define CASE_GET_SDRAM_PARAM(x) \
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case token_##x:\
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*value = params->x; \
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break
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#define CASE_SET_SDRAM_PARAM(x) \
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case token_##x:\
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params->x = value; \
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break
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#define CASE_GET_DEV_PARAM(dev, x) \
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case token_##dev##_##x:\
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*value = bct->dev_params[index].dev##_params.x; \
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break
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#define CASE_SET_DEV_PARAM(dev, x) \
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case token_##dev##_##x:\
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bct->dev_params[index].dev##_params.x = value; \
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break
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#define CASE_GET_BL_PARAM(x) \
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case token_bl_##x:\
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*data = bct_ptr->bootloader[set].x; \
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break
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#define CASE_SET_BL_PARAM(x) \
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case token_bl_##x:\
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bct_ptr->bootloader[set].x = *data; \
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break
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#define CASE_GET_NVU32(id) \
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case token_##id:\
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if (bct == NULL) return -ENODATA; \
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*data = bct_ptr->id; \
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break
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#define CASE_GET_CONST(id, val) \
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case token_##id:\
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*data = val; \
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break
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#define CASE_GET_CONST_PREFIX(id, val_prefix) \
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case token_##id:\
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*data = val_prefix##_##id; \
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break
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#define CASE_SET_NVU32(id) \
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case token_##id:\
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bct_ptr->id = data; \
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break
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#define CASE_GET_DATA(id, size) \
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case token_##id:\
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if (*length < size) return -ENODATA;\
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memcpy(data, &(bct_ptr->id), size); \
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*length = size;\
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break
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#define CASE_SET_DATA(id, size) \
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case token_##id:\
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if (length < size) return -ENODATA;\
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memcpy(&(bct_ptr->id), data, size); \
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break
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#define DEFAULT() \
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default : \
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printf("Unexpected token %d at line %d\n", \
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token, __LINE__); \
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return 1
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int
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t20_set_dev_param(build_image_context *context,
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u_int32_t index,
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parse_token token,
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u_int32_t value)
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{
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nvboot_config_table *bct = NULL;
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bct = (nvboot_config_table *)(context->bct);
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assert(context != NULL);
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assert(bct != NULL);
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bct->num_param_sets = NV_MAX(bct->num_param_sets, index + 1);
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switch (token) {
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CASE_SET_DEV_PARAM(nand, clock_divider);
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CASE_SET_DEV_PARAM(nand, nand_timing);
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CASE_SET_DEV_PARAM(nand, nand_timing2);
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CASE_SET_DEV_PARAM(nand, block_size_log2);
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CASE_SET_DEV_PARAM(nand, page_size_log2);
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CASE_SET_DEV_PARAM(sdmmc, clock_divider);
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CASE_SET_DEV_PARAM(sdmmc, data_width);
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CASE_SET_DEV_PARAM(sdmmc, max_power_class_supported);
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CASE_SET_DEV_PARAM(spiflash, clock_source);
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CASE_SET_DEV_PARAM(spiflash, clock_divider);
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CASE_SET_DEV_PARAM(spiflash, read_command_type_fast);
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case token_dev_type:
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bct->dev_type[index] = value;
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break;
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default:
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return -ENODATA;
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}
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return 0;
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}
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int
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t20_get_dev_param(build_image_context *context,
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u_int32_t index,
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parse_token token,
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u_int32_t *value)
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{
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nvboot_config_table *bct = NULL;
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bct = (nvboot_config_table *)(context->bct);
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assert(context != NULL);
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assert(bct != NULL);
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switch (token) {
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CASE_GET_DEV_PARAM(nand, clock_divider);
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CASE_GET_DEV_PARAM(nand, nand_timing);
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CASE_GET_DEV_PARAM(nand, nand_timing2);
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CASE_GET_DEV_PARAM(nand, block_size_log2);
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CASE_GET_DEV_PARAM(nand, page_size_log2);
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CASE_GET_DEV_PARAM(sdmmc, clock_divider);
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CASE_GET_DEV_PARAM(sdmmc, data_width);
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CASE_GET_DEV_PARAM(sdmmc, max_power_class_supported);
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CASE_GET_DEV_PARAM(spiflash, clock_source);
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CASE_GET_DEV_PARAM(spiflash, clock_divider);
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CASE_GET_DEV_PARAM(spiflash, read_command_type_fast);
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case token_dev_type:
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*value = bct->dev_type[index];
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break;
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default:
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return -ENODATA;
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}
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return 0;
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}
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int
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t20_set_sdram_param(build_image_context *context,
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u_int32_t index,
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parse_token token,
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u_int32_t value)
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{
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nvboot_sdram_params *params;
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nvboot_config_table *bct = NULL;
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bct = (nvboot_config_table *)(context->bct);
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assert(context != NULL);
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assert(bct != NULL);
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params = &(bct->sdram_params[index]);
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/* Update the number of SDRAM parameter sets. */
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bct->num_sdram_sets = NV_MAX(bct->num_sdram_sets, index + 1);
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switch (token) {
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CASE_SET_SDRAM_PARAM(memory_type);
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CASE_SET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl);
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CASE_SET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl);
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CASE_SET_SDRAM_PARAM(pllm_input_divider);
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CASE_SET_SDRAM_PARAM(pllm_feedback_divider);
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CASE_SET_SDRAM_PARAM(pllm_post_divider);
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CASE_SET_SDRAM_PARAM(pllm_stable_time);
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CASE_SET_SDRAM_PARAM(emc_clock_divider);
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CASE_SET_SDRAM_PARAM(emc_auto_cal_interval);
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CASE_SET_SDRAM_PARAM(emc_auto_cal_config);
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CASE_SET_SDRAM_PARAM(emc_auto_cal_wait);
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CASE_SET_SDRAM_PARAM(emc_pin_program_wait);
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CASE_SET_SDRAM_PARAM(emc_rc);
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CASE_SET_SDRAM_PARAM(emc_rfc);
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CASE_SET_SDRAM_PARAM(emc_ras);
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CASE_SET_SDRAM_PARAM(emc_rp);
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CASE_SET_SDRAM_PARAM(emc_r2w);
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CASE_SET_SDRAM_PARAM(emc_w2r);
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CASE_SET_SDRAM_PARAM(emc_r2p);
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CASE_SET_SDRAM_PARAM(emc_w2p);
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CASE_SET_SDRAM_PARAM(emc_rd_rcd);
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CASE_SET_SDRAM_PARAM(emc_wr_rcd);
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CASE_SET_SDRAM_PARAM(emc_rrd);
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CASE_SET_SDRAM_PARAM(emc_rext);
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CASE_SET_SDRAM_PARAM(emc_wdv);
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CASE_SET_SDRAM_PARAM(emc_quse);
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CASE_SET_SDRAM_PARAM(emc_qrst);
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CASE_SET_SDRAM_PARAM(emc_qsafe);
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CASE_SET_SDRAM_PARAM(emc_rdv);
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CASE_SET_SDRAM_PARAM(emc_refresh);
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CASE_SET_SDRAM_PARAM(emc_burst_refresh_num);
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CASE_SET_SDRAM_PARAM(emc_pdex2wr);
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CASE_SET_SDRAM_PARAM(emc_pdex2rd);
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CASE_SET_SDRAM_PARAM(emc_pchg2pden);
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CASE_SET_SDRAM_PARAM(emc_act2pden);
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CASE_SET_SDRAM_PARAM(emc_ar2pden);
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CASE_SET_SDRAM_PARAM(emc_rw2pden);
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CASE_SET_SDRAM_PARAM(emc_txsr);
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CASE_SET_SDRAM_PARAM(emc_tcke);
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CASE_SET_SDRAM_PARAM(emc_tfaw);
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CASE_SET_SDRAM_PARAM(emc_trpab);
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CASE_SET_SDRAM_PARAM(emc_tclkstable);
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CASE_SET_SDRAM_PARAM(emc_tclkstop);
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CASE_SET_SDRAM_PARAM(emc_trefbw);
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CASE_SET_SDRAM_PARAM(emc_quse_extra);
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CASE_SET_SDRAM_PARAM(emc_fbio_cfg1);
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CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly);
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CASE_SET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb);
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CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly);
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CASE_SET_SDRAM_PARAM(emc_fbio_quse_dly_msb);
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CASE_SET_SDRAM_PARAM(emc_fbio_cfg5);
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CASE_SET_SDRAM_PARAM(emc_fbio_cfg6);
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CASE_SET_SDRAM_PARAM(emc_fbio_spare);
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CASE_SET_SDRAM_PARAM(emc_mrs);
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CASE_SET_SDRAM_PARAM(emc_emrs);
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CASE_SET_SDRAM_PARAM(emc_mrw1);
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CASE_SET_SDRAM_PARAM(emc_mrw2);
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CASE_SET_SDRAM_PARAM(emc_mrw3);
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CASE_SET_SDRAM_PARAM(emc_mrw_reset_command);
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CASE_SET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
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CASE_SET_SDRAM_PARAM(emc_adr_cfg);
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CASE_SET_SDRAM_PARAM(emc_adr_cfg1);
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CASE_SET_SDRAM_PARAM(mc_emem_cfg);
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CASE_SET_SDRAM_PARAM(mc_lowlatency_config);
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CASE_SET_SDRAM_PARAM(emc_cfg);
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CASE_SET_SDRAM_PARAM(emc_cfg2);
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CASE_SET_SDRAM_PARAM(emc_dbg);
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CASE_SET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl);
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CASE_SET_SDRAM_PARAM(emc_cfg_dig_dll);
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CASE_SET_SDRAM_PARAM(emc_dll_xform_dqs);
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CASE_SET_SDRAM_PARAM(emc_dll_xform_quse);
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CASE_SET_SDRAM_PARAM(warm_boot_wait);
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CASE_SET_SDRAM_PARAM(emc_ctt_term_ctrl);
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CASE_SET_SDRAM_PARAM(emc_odt_write);
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CASE_SET_SDRAM_PARAM(emc_odt_read);
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CASE_SET_SDRAM_PARAM(emc_zcal_ref_cnt);
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CASE_SET_SDRAM_PARAM(emc_zcal_wait_cnt);
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CASE_SET_SDRAM_PARAM(emc_zcal_mrw_cmd);
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CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll);
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CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev0);
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CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_dev1);
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CASE_SET_SDRAM_PARAM(emc_mrw_zq_init_wait);
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CASE_SET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
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CASE_SET_SDRAM_PARAM(emc_emrs_emr2);
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CASE_SET_SDRAM_PARAM(emc_emrs_emr3);
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CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
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CASE_SET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
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CASE_SET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
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CASE_SET_SDRAM_PARAM(emc_ddr2_wait);
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CASE_SET_SDRAM_PARAM(emc_cfg_clktrim0);
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CASE_SET_SDRAM_PARAM(emc_cfg_clktrim1);
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CASE_SET_SDRAM_PARAM(emc_cfg_clktrim2);
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CASE_SET_SDRAM_PARAM(pmc_ddr_pwr);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl);
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CASE_SET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl);
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DEFAULT();
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}
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return 0;
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}
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int
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t20_get_sdram_param(build_image_context *context,
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u_int32_t index,
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parse_token token,
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u_int32_t *value)
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{
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nvboot_sdram_params *params;
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nvboot_config_table *bct = NULL;
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bct = (nvboot_config_table *)(context->bct);
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assert(context != NULL);
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assert(bct != NULL);
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params = &(bct->sdram_params[index]);
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switch (token) {
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CASE_GET_SDRAM_PARAM(memory_type);
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CASE_GET_SDRAM_PARAM(pllm_charge_pump_setup_ctrl);
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CASE_GET_SDRAM_PARAM(pllm_loop_filter_setup_ctrl);
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CASE_GET_SDRAM_PARAM(pllm_input_divider);
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CASE_GET_SDRAM_PARAM(pllm_feedback_divider);
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CASE_GET_SDRAM_PARAM(pllm_post_divider);
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CASE_GET_SDRAM_PARAM(pllm_stable_time);
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CASE_GET_SDRAM_PARAM(emc_clock_divider);
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CASE_GET_SDRAM_PARAM(emc_auto_cal_interval);
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CASE_GET_SDRAM_PARAM(emc_auto_cal_config);
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CASE_GET_SDRAM_PARAM(emc_auto_cal_wait);
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CASE_GET_SDRAM_PARAM(emc_pin_program_wait);
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CASE_GET_SDRAM_PARAM(emc_rc);
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CASE_GET_SDRAM_PARAM(emc_rfc);
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CASE_GET_SDRAM_PARAM(emc_ras);
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CASE_GET_SDRAM_PARAM(emc_rp);
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CASE_GET_SDRAM_PARAM(emc_r2w);
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CASE_GET_SDRAM_PARAM(emc_w2r);
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CASE_GET_SDRAM_PARAM(emc_r2p);
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CASE_GET_SDRAM_PARAM(emc_w2p);
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CASE_GET_SDRAM_PARAM(emc_rd_rcd);
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CASE_GET_SDRAM_PARAM(emc_wr_rcd);
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CASE_GET_SDRAM_PARAM(emc_rrd);
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CASE_GET_SDRAM_PARAM(emc_rext);
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CASE_GET_SDRAM_PARAM(emc_wdv);
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CASE_GET_SDRAM_PARAM(emc_quse);
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CASE_GET_SDRAM_PARAM(emc_qrst);
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CASE_GET_SDRAM_PARAM(emc_qsafe);
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CASE_GET_SDRAM_PARAM(emc_rdv);
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CASE_GET_SDRAM_PARAM(emc_refresh);
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CASE_GET_SDRAM_PARAM(emc_burst_refresh_num);
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CASE_GET_SDRAM_PARAM(emc_pdex2wr);
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CASE_GET_SDRAM_PARAM(emc_pdex2rd);
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CASE_GET_SDRAM_PARAM(emc_pchg2pden);
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CASE_GET_SDRAM_PARAM(emc_act2pden);
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CASE_GET_SDRAM_PARAM(emc_ar2pden);
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CASE_GET_SDRAM_PARAM(emc_rw2pden);
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CASE_GET_SDRAM_PARAM(emc_txsr);
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CASE_GET_SDRAM_PARAM(emc_tcke);
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CASE_GET_SDRAM_PARAM(emc_tfaw);
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CASE_GET_SDRAM_PARAM(emc_trpab);
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CASE_GET_SDRAM_PARAM(emc_tclkstable);
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CASE_GET_SDRAM_PARAM(emc_tclkstop);
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CASE_GET_SDRAM_PARAM(emc_trefbw);
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CASE_GET_SDRAM_PARAM(emc_quse_extra);
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CASE_GET_SDRAM_PARAM(emc_fbio_cfg1);
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CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly);
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CASE_GET_SDRAM_PARAM(emc_fbio_dqsib_dly_msb);
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CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly);
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CASE_GET_SDRAM_PARAM(emc_fbio_quse_dly_msb);
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CASE_GET_SDRAM_PARAM(emc_fbio_cfg5);
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CASE_GET_SDRAM_PARAM(emc_fbio_cfg6);
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CASE_GET_SDRAM_PARAM(emc_fbio_spare);
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CASE_GET_SDRAM_PARAM(emc_mrs);
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CASE_GET_SDRAM_PARAM(emc_emrs);
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CASE_GET_SDRAM_PARAM(emc_mrw1);
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CASE_GET_SDRAM_PARAM(emc_mrw2);
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CASE_GET_SDRAM_PARAM(emc_mrw3);
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CASE_GET_SDRAM_PARAM(emc_mrw_reset_command);
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CASE_GET_SDRAM_PARAM(emc_mrw_reset_ninit_wait);
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CASE_GET_SDRAM_PARAM(emc_adr_cfg);
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CASE_GET_SDRAM_PARAM(emc_adr_cfg1);
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CASE_GET_SDRAM_PARAM(mc_emem_cfg);
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CASE_GET_SDRAM_PARAM(mc_lowlatency_config);
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CASE_GET_SDRAM_PARAM(emc_cfg);
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CASE_GET_SDRAM_PARAM(emc_cfg2);
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CASE_GET_SDRAM_PARAM(emc_dbg);
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CASE_GET_SDRAM_PARAM(ahb_arbitration_xbar_ctrl);
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CASE_GET_SDRAM_PARAM(emc_cfg_dig_dll);
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CASE_GET_SDRAM_PARAM(emc_dll_xform_dqs);
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CASE_GET_SDRAM_PARAM(emc_dll_xform_quse);
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CASE_GET_SDRAM_PARAM(warm_boot_wait);
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CASE_GET_SDRAM_PARAM(emc_ctt_term_ctrl);
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CASE_GET_SDRAM_PARAM(emc_odt_write);
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CASE_GET_SDRAM_PARAM(emc_odt_read);
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CASE_GET_SDRAM_PARAM(emc_zcal_ref_cnt);
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CASE_GET_SDRAM_PARAM(emc_zcal_wait_cnt);
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CASE_GET_SDRAM_PARAM(emc_zcal_mrw_cmd);
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CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll);
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CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev0);
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CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_dev1);
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CASE_GET_SDRAM_PARAM(emc_mrw_zq_init_wait);
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CASE_GET_SDRAM_PARAM(emc_mrs_reset_dll_wait);
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CASE_GET_SDRAM_PARAM(emc_emrs_emr2);
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CASE_GET_SDRAM_PARAM(emc_emrs_emr3);
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CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_dll_enable);
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CASE_GET_SDRAM_PARAM(emc_mrs_ddr2_dll_reset);
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CASE_GET_SDRAM_PARAM(emc_emrs_ddr2_ocd_calib);
|
|
CASE_GET_SDRAM_PARAM(emc_ddr2_wait);
|
|
CASE_GET_SDRAM_PARAM(emc_cfg_clktrim0);
|
|
CASE_GET_SDRAM_PARAM(emc_cfg_clktrim1);
|
|
CASE_GET_SDRAM_PARAM(emc_cfg_clktrim2);
|
|
CASE_GET_SDRAM_PARAM(pmc_ddr_pwr);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfga_pad_ctrl);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgc_pad_ctrl2);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2cfgd_pad_ctrl2);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2clkcfg_Pad_ctrl);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2comp_pad_ctrl);
|
|
CASE_GET_SDRAM_PARAM(apb_misc_gp_xm2vttgen_pad_ctrl);
|
|
DEFAULT();
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
t20_getbl_param(u_int32_t set,
|
|
parse_token id,
|
|
u_int32_t *data,
|
|
u_int8_t *bct)
|
|
{
|
|
nvboot_config_table *bct_ptr = (nvboot_config_table *)bct;
|
|
|
|
if (set >= NVBOOT_MAX_BOOTLOADERS)
|
|
return -ENODATA;
|
|
if (data == NULL || bct == NULL)
|
|
return -ENODATA;
|
|
|
|
switch (id) {
|
|
CASE_GET_BL_PARAM(version);
|
|
CASE_GET_BL_PARAM(start_blk);
|
|
CASE_GET_BL_PARAM(start_page);
|
|
CASE_GET_BL_PARAM(length);
|
|
CASE_GET_BL_PARAM(load_addr);
|
|
CASE_GET_BL_PARAM(entry_point);
|
|
CASE_GET_BL_PARAM(attribute);
|
|
|
|
case token_bl_crypto_hash:
|
|
memcpy(data,
|
|
&(bct_ptr->bootloader[set].crypto_hash),
|
|
sizeof(nvboot_hash));
|
|
break;
|
|
|
|
default:
|
|
return -ENODATA;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
t20_setbl_param(u_int32_t set,
|
|
parse_token id,
|
|
u_int32_t *data,
|
|
u_int8_t *bct)
|
|
{
|
|
nvboot_config_table *bct_ptr = (nvboot_config_table *)bct;
|
|
|
|
if (set >= NVBOOT_MAX_BOOTLOADERS)
|
|
return -ENODATA;
|
|
if (data == NULL || bct == NULL)
|
|
return -ENODATA;
|
|
|
|
switch (id) {
|
|
CASE_SET_BL_PARAM(version);
|
|
CASE_SET_BL_PARAM(start_blk);
|
|
CASE_SET_BL_PARAM(start_page);
|
|
CASE_SET_BL_PARAM(length);
|
|
CASE_SET_BL_PARAM(load_addr);
|
|
CASE_SET_BL_PARAM(entry_point);
|
|
CASE_SET_BL_PARAM(attribute);
|
|
|
|
case token_bl_crypto_hash:
|
|
memcpy(&(bct_ptr->bootloader[set].crypto_hash),
|
|
data,
|
|
sizeof(nvboot_hash));
|
|
break;
|
|
|
|
default:
|
|
return -ENODATA;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
t20_bct_get_value(parse_token id, u_int32_t *data, u_int8_t *bct)
|
|
{
|
|
nvboot_config_table *bct_ptr = (nvboot_config_table *)bct;
|
|
nvboot_config_table samplebct; /* Used for computing offsets. */
|
|
|
|
/*
|
|
* Note: Not all queries require use of the BCT, so testing for a
|
|
* valid BCT is distributed within the code.
|
|
*/
|
|
if (data == NULL)
|
|
return -ENODATA;
|
|
|
|
switch (id) {
|
|
/*
|
|
* Simple BCT fields
|
|
*/
|
|
CASE_GET_NVU32(boot_data_version);
|
|
CASE_GET_NVU32(block_size_log2);
|
|
CASE_GET_NVU32(page_size_log2);
|
|
CASE_GET_NVU32(partition_size);
|
|
CASE_GET_NVU32(num_param_sets);
|
|
CASE_GET_NVU32(num_sdram_sets);
|
|
CASE_GET_NVU32(bootloader_used);
|
|
CASE_GET_NVU32(odm_data);
|
|
|
|
/*
|
|
* Constants.
|
|
*/
|
|
|
|
CASE_GET_CONST(bootloaders_max, NVBOOT_MAX_BOOTLOADERS);
|
|
CASE_GET_CONST(reserved_size, NVBOOT_BCT_RESERVED_SIZE);
|
|
|
|
case token_reserved_offset:
|
|
*data = (u_int8_t *)&(samplebct.reserved)
|
|
- (u_int8_t *)&samplebct;
|
|
break;
|
|
|
|
case token_bct_size:
|
|
*data = sizeof(nvboot_config_table);
|
|
break;
|
|
|
|
CASE_GET_CONST(hash_size, sizeof(nvboot_hash));
|
|
|
|
case token_crypto_offset:
|
|
/* Offset to region in BCT to encrypt & sign */
|
|
*data = (u_int8_t *)&(samplebct.random_aes_blk)
|
|
- (u_int8_t *)&samplebct;
|
|
break;
|
|
|
|
case token_crypto_length:
|
|
/* size of region in BCT to encrypt & sign */
|
|
*data = sizeof(nvboot_config_table) - sizeof(nvboot_hash);
|
|
break;
|
|
|
|
CASE_GET_CONST(max_bct_search_blks, NVBOOT_MAX_BCT_SEARCH_BLOCKS);
|
|
|
|
CASE_GET_CONST_PREFIX(dev_type_nand, nvboot);
|
|
CASE_GET_CONST_PREFIX(dev_type_sdmmc, nvboot);
|
|
CASE_GET_CONST_PREFIX(dev_type_spi, nvboot);
|
|
CASE_GET_CONST_PREFIX(sdmmc_data_width_4bit, nvboot);
|
|
CASE_GET_CONST_PREFIX(sdmmc_data_width_8bit, nvboot);
|
|
CASE_GET_CONST_PREFIX(spi_clock_source_pllp_out0, nvboot);
|
|
CASE_GET_CONST_PREFIX(spi_clock_source_pllc_out0, nvboot);
|
|
CASE_GET_CONST_PREFIX(spi_clock_source_pllm_out0, nvboot);
|
|
CASE_GET_CONST_PREFIX(spi_clock_source_clockm, nvboot);
|
|
|
|
CASE_GET_CONST_PREFIX(memory_type_none, nvboot);
|
|
CASE_GET_CONST_PREFIX(memory_type_ddr, nvboot);
|
|
CASE_GET_CONST_PREFIX(memory_type_lpddr, nvboot);
|
|
CASE_GET_CONST_PREFIX(memory_type_ddr2, nvboot);
|
|
CASE_GET_CONST_PREFIX(memory_type_lpddr2, nvboot);
|
|
|
|
default:
|
|
return -ENODATA;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
t20_bct_set_value(parse_token id, u_int32_t data, u_int8_t *bct)
|
|
{
|
|
nvboot_config_table *bct_ptr = (nvboot_config_table *)bct;
|
|
|
|
if (bct == NULL)
|
|
return -ENODATA;
|
|
|
|
switch (id) {
|
|
/*
|
|
* Simple BCT fields
|
|
*/
|
|
CASE_SET_NVU32(boot_data_version);
|
|
CASE_SET_NVU32(block_size_log2);
|
|
CASE_SET_NVU32(page_size_log2);
|
|
CASE_SET_NVU32(partition_size);
|
|
CASE_SET_NVU32(num_param_sets);
|
|
CASE_SET_NVU32(num_sdram_sets);
|
|
CASE_SET_NVU32(bootloader_used);
|
|
CASE_SET_NVU32(odm_data);
|
|
|
|
default:
|
|
return -ENODATA;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
t20_bct_set_data(parse_token id,
|
|
u_int8_t *data,
|
|
u_int32_t length,
|
|
u_int8_t *bct)
|
|
{
|
|
nvboot_config_table *bct_ptr = (nvboot_config_table *)bct;
|
|
|
|
if (data == NULL || bct == NULL)
|
|
return -ENODATA;
|
|
|
|
switch (id) {
|
|
|
|
CASE_SET_DATA(crypto_hash, sizeof(nvboot_hash));
|
|
|
|
default:
|
|
return -ENODATA;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void t20_init_bad_block_table(build_image_context *context)
|
|
{
|
|
u_int32_t bytes_per_entry;
|
|
nvboot_badblock_table *table;
|
|
nvboot_config_table *bct;
|
|
|
|
bct = (nvboot_config_table *)(context->bct);
|
|
|
|
assert(context != NULL);
|
|
assert(bct != NULL);
|
|
|
|
table = &bct->badblock_table;
|
|
|
|
bytes_per_entry = ICEIL(context->partition_size,
|
|
NVBOOT_BAD_BLOCK_TABLE_SIZE);
|
|
table->block_size_log2 = context->block_size_log2;
|
|
table->virtual_blk_size_log2 = NV_MAX(ceil_log2(bytes_per_entry),
|
|
table->block_size_log2);
|
|
table->entries_used = iceil_log2(context->partition_size,
|
|
table->virtual_blk_size_log2);
|
|
}
|
|
|
|
cbootimage_soc_config tegra20_config = {
|
|
.init_bad_block_table = t20_init_bad_block_table,
|
|
.set_dev_param = t20_set_dev_param,
|
|
.get_dev_param = t20_get_dev_param,
|
|
.set_sdram_param = t20_set_sdram_param,
|
|
.get_sdram_param = t20_get_sdram_param,
|
|
.setbl_param = t20_setbl_param,
|
|
.getbl_param = t20_getbl_param,
|
|
.set_value = t20_bct_set_value,
|
|
.get_value = t20_bct_get_value,
|
|
.set_data = t20_bct_set_data,
|
|
|
|
.devtype_table = s_devtype_table_t20,
|
|
.sdmmc_data_width_table = s_sdmmc_data_width_table_t20,
|
|
.spi_clock_source_table = s_spi_clock_source_table_t20,
|
|
.nvboot_memory_type_table = s_nvboot_memory_type_table_t20,
|
|
.sdram_field_table = s_sdram_field_table_t20,
|
|
.nand_table = s_nand_table_t20,
|
|
.sdmmc_table = s_sdmmc_table_t20,
|
|
.spiflash_table = s_spiflash_table_t20,
|
|
.device_type_table = s_device_type_table_t20,
|
|
};
|
|
|
|
void t20_get_soc_config(build_image_context *context,
|
|
cbootimage_soc_config **soc_config)
|
|
{
|
|
context->boot_data_version = BOOTDATA_VERSION_T20;
|
|
*soc_config = &tegra20_config;
|
|
}
|
|
|
|
int if_bct_is_t20_get_soc_config(build_image_context *context,
|
|
cbootimage_soc_config **soc_config)
|
|
{
|
|
nvboot_config_table * bct = (nvboot_config_table *) context->bct;
|
|
|
|
if (bct->boot_data_version == BOOTDATA_VERSION_T20)
|
|
{
|
|
t20_get_soc_config(context, soc_config);
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|