261 lines
6.0 KiB
ArmAsm
261 lines
6.0 KiB
ArmAsm
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <mach/imx-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <asm/cache-l2x0.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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/* Assuming 24MHz input clock */
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#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
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#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
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#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
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.section ".text_bare_init","ax"
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ARM_PPMRR: .word 0x40000015
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L2CACHE_PARAM: .word 0x00030024
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CCM_CCMR_W: .word 0x003F4208
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CCM_PDR0_W: .word 0x00801000
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MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
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MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
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PPCTL_PARAM_W: .word PPCTL_PARAM_300
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CCM_BASE_ADDR_W: .word IMX_CCM_BASE
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/*
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* End of ARM1136 init
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*/
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#define MX25_CCM_MCR 0x64
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#define MX25_CCM_CGR0 0x0c
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#define MX25_CCM_CGR1 0x10
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#define MX25_CCM_CGR2 0x14
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ldr r0, CCM_BASE_ADDR_W
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/* default CLKO to 1/32 of the ARM core */
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ldr r1, [r0, #MX25_CCM_MCR]
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bic r1, r1, #0x00F00000
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bic r1, r1, #0x7F000000
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mov r2, #0x5F000000
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add r2, r2, #0x00200000
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orr r1, r1, r2
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str r1, [r0, #MX25_CCM_MCR]
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/* enable all the clocks */
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writel(0x1FFFFFFF, IMX_CCM_BASE + MX25_CCM_CGR0)
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writel(0xFFFFFFFF, IMX_CCM_BASE + MX25_CCM_CGR1)
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writel(0x000FDFFF, IMX_CCM_BASE + MX25_CCM_CGR2)
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writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR)
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x80000000
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bls 1f
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cmp pc, #0x90000000
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bhi 1f
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mov pc, lr
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1:
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ldr r0, ESDCTL_BASE_W
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mov r3, #0x2000
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str r3, [r0, #0x0]
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str r3, [r0, #0x8]
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mov r12, #0x00
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mov r2, #0x1 /* mDDR */
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mov r1, #IMX_SDRAM_CS0
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bl setup_sdram_bank
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// cmp r3, #0x0
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// orreq r12, r12, #1
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// eorne r2, r2, #0x1
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// blne setup_sdram_bank
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ldr r3, ESDCTL_DELAY5
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str r3, [r0, #0x30]
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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bls ret
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cmp pc, r2
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bhi ret
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/* Move ourselves out of NFC SRAM */
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ldr r1, =TEXT_BASE
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copy_loop:
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ldmia r0!, {r3-r9} /* copy from source address [r0] */
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stmia r1!, {r3-r9} /* copy to target address [r1] */
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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ldr pc, =1f /* Jump to SDRAM */
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1:
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bl nand_boot /* Load U-Boot from NAND Flash */
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ldr r1, =IMX_NFC_BASE - TEXT_BASE
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sub r10, r10, r1 /* adjust return address from NFC SRAM */
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/* to SDRAM */
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#endif /* CONFIG_NAND_IMX_BOOT */
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ret:
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mov pc, r10
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/*
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* r0: control base, r1: ram bank base
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* r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
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*/
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setup_sdram_bank:
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mov r3, #0xE /* 0xA + 0x4 */
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tst r2, #0x1
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orreq r3, r3, #0x300 /* DDR2 */
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str r3, [r0, #0x10]
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bic r3, r3, #0x00A
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str r3, [r0, #0x10]
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beq 2f
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mov r3, #0x20000
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1: subs r3, r3, #1
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bne 1b
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2: adr r4, ESDCTL_CONFIG
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tst r2, #0x1
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ldreq r3, [r4, #0x0]
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ldrne r3, [r4, #0x4]
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cmp r1, #IMX_SDRAM_CS1
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strlo r3, [r0, #0x4]
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strhs r3, [r0, #0xC]
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ldr r3, ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, RAM_PARAM1_MDDR
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strb r3, [r1, r4]
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tst r2, #0x1
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bne skip_set_mode
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cmp r1, #IMX_SDRAM_CS1
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ldr r3, ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, RAM_PARAM4_MDDR
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strb r3, [r1, r4]
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ldr r4, RAM_PARAM5_MDDR
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strb r3, [r1, r4]
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ldr r4, RAM_PARAM3_MDDR
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strb r3, [r1, r4]
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ldr r4, RAM_PARAM2_MDDR
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strb r3, [r1, r4]
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ldr r3, ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, RAM_PARAM1_MDDR
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strb r3, [r1, r4]
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skip_set_mode:
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cmp r1, #IMX_SDRAM_CS1
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ldr r3, ESDCTL_0xA2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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strb r3, [r1]
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strb r3, [r1]
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ldr r3, ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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adr r4, RAM_PARAM6_MDDR
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tst r2, #0x1
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ldreq r4, [r4, #0x0]
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ldrne r4, [r4, #0x4]
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mov r3, #0xDA
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strb r3, [r1, r4]
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ldreq r4, RAM_PARAM7_MDDR
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streqb r3, [r1, r4]
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adr r4, RAM_PARAM3_MDDR
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ldreq r4, [r4, #0x0]
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ldrne r4, [r4, #0x4]
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strb r3, [r1, r4]
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cmp r1, #IMX_SDRAM_CS1
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ldr r3, ESDCTL_0x82226080
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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moveq r4, #0x20000
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movne r4, #0x200
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1: subs r4, r4, #1
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bne 1b
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str r3, [r1, #0x100]
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ldr r4, [r1, #0x100]
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cmp r3, r4
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movne r3, #1
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moveq r3, #0
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mov pc, lr
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RAM_PARAM1_MDDR: .word 0x00000400
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RAM_PARAM2_MDDR: .word 0x00000333
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RAM_PARAM3_MDDR: .word 0x02000400
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.word 0x02000000
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RAM_PARAM4_MDDR: .word 0x04000000
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RAM_PARAM5_MDDR: .word 0x06000000
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RAM_PARAM6_MDDR: .word 0x00000233
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.word 0x00000033
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RAM_PARAM7_MDDR: .word 0x02000780
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ESDCTL_0x92220000: .word 0x92210000
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ESDCTL_0xA2220000: .word 0xA2210000
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ESDCTL_0xB2220000: .word 0xB2210000
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ESDCTL_0x82226080: .word 0x82216080
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ESDCTL_CONFIG: .word 0x007FFC3F
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.word 0x007FFC3F
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ESDCTL_DELAY5: .word 0x00F49F00
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ESDCTL_BASE_W: .word IMX_ESD_BASE
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