164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <asm-generic/div64.h>
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#include "clk.h"
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/* PLL Register Offsets */
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#define MXC_PLL_DP_CTL 0x00
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#define MXC_PLL_DP_CONFIG 0x04
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#define MXC_PLL_DP_OP 0x08
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#define MXC_PLL_DP_MFD 0x0C
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#define MXC_PLL_DP_MFN 0x10
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#define MXC_PLL_DP_MFNMINUS 0x14
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#define MXC_PLL_DP_MFNPLUS 0x18
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#define MXC_PLL_DP_HFS_OP 0x1C
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#define MXC_PLL_DP_HFS_MFD 0x20
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#define MXC_PLL_DP_HFS_MFN 0x24
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#define MXC_PLL_DP_MFN_TOGC 0x28
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#define MXC_PLL_DP_DESTAT 0x2c
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/* PLL Register Bit definitions */
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#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
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#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
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#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
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#define MXC_PLL_DP_CTL_ADE 0x800
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#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
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#define MXC_PLL_DP_CTL_HFSM 0x80
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#define MXC_PLL_DP_CTL_PRE 0x40
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#define MXC_PLL_DP_CTL_UPEN 0x20
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#define MXC_PLL_DP_CTL_RST 0x10
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#define MXC_PLL_DP_CTL_RCP 0x8
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#define MXC_PLL_DP_CTL_PLM 0x4
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#define MXC_PLL_DP_CTL_BRM0 0x2
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#define MXC_PLL_DP_CTL_LRF 0x1
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#define MXC_PLL_DP_CONFIG_BIST 0x8
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#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
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#define MXC_PLL_DP_CONFIG_AREN 0x2
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#define MXC_PLL_DP_CONFIG_LDREQ 0x1
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#define MXC_PLL_DP_OP_MFI_OFFSET 4
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#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
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#define MXC_PLL_DP_OP_PDF_OFFSET 0
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#define MXC_PLL_DP_OP_PDF_MASK 0xF
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#define MXC_PLL_DP_MFD_OFFSET 0
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#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
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#define MXC_PLL_DP_MFN_OFFSET 0x0
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#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
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#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
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#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
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#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
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#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
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#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
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#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
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#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
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struct clk_pllv2 {
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struct clk clk;
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void __iomem *reg;
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const char *parent;
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};
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static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
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u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
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{
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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unsigned long dbl;
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uint64_t temp;
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dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
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pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
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mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
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mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
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/* Sign extend to 32-bits */
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if (mfn >= 0x04000000) {
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mfn |= 0xFC000000;
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mfn_abs = -mfn;
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}
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ref_clk = 2 * parent_rate;
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if (dbl != 0)
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ref_clk *= 2;
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ref_clk /= (pdf + 1);
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temp = (u64) ref_clk * mfn_abs;
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do_div(temp, mfd + 1);
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if (mfn < 0)
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temp = -temp;
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temp = (ref_clk * mfi) + temp;
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return temp;
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}
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static unsigned long clk_pllv2_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
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void __iomem *pllbase;
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struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk);
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pllbase = pll->reg;
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dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
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dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
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dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
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dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
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return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
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}
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struct clk_ops clk_pllv2_ops = {
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.recalc_rate = clk_pllv2_recalc_rate,
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};
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base)
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{
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struct clk_pllv2 *pll = xzalloc(sizeof(*pll));
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int ret;
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pll->parent = parent;
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pll->reg = base;
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pll->clk.ops = &clk_pllv2_ops;
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pll->clk.name = name;
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pll->clk.parent_names = &pll->parent;
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pll->clk.num_parents = 1;
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ret = clk_register(&pll->clk);
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if (ret) {
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free(pll);
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return ERR_PTR(ret);
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}
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return &pll->clk;
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}
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