67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
#ifndef __CONFIG_H
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#define __CONFIG_H
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#define MASTER_PLL_MUL 39
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#define MASTER_PLL_DIV 4
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/* clocks */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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(0x3e << 8) | /* PLL Counter */ \
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(0 << 14) | /* Divider A */ \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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/* PCK/2 = MCK Master Clock from SLOW */
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#define CONFIG_SYS_MCKR2_VAL1 \
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(AT91_PMC_CSS_SLOW | \
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AT91RM9200_PMC_MDIV_2) \
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/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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#define CONFIG_SYS_MCKR2_VAL2 \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91RM9200_PMC_MDIV_3 |\
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AT91_PMC_PDIV_1)
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/* flash */
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#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
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#define CONFIG_SYS_SMC_CSR0_VAL \
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(AT91_SMC_NWS_(4) | /* Number of Wait States */ \
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AT91_SMC_WSEN | /* Wait State Enable */ \
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AT91_SMC_TDF_(2) | /* Data Float Time */ \
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AT91_SMC_BAT | /* Byte Access Type */ \
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AT91_SMC_DBW_16) /* Data Bus Width */
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/* sdram */
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#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
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#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
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#define CONFIG_SYS_EBI_CSA_VAL \
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(AT91_EBI_CS0A_SMC | \
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AT91_EBI_CS1A_SDRAMC | \
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AT91_EBI_CS3A_SMC | \
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AT91_EBI_CS4A_SMC) \
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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/* SDRAMC_CR - Configuration register*/
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#define CONFIG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_12 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_2 | \
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(1 << 8) | /* Write Recovery Delay */ \
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(12 << 12) | /* Row Cycle Delay */ \
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(8 << 16) | /* Row Precharge Delay */ \
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(8 << 20) | /* Row to Column Delay */ \
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(1 << 24) | /* Active to Precharge Delay */ \
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(2 << 28)) /* Exit Self Refresh to Active Delay */
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#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#endif /* __CONFIG_H */
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