194 lines
6.4 KiB
C
194 lines
6.4 KiB
C
#include <init.h>
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#include <io.h>
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#include <sizes.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/control.h>
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#include <mach/generic.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap3-generic.h>
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#include <mach/omap3-mux.h>
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#include <mach/sdrc.h>
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#include <mach/syslib.h>
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#include <mach/sys_info.h>
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/**
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* @brief Do the pin muxing required for Board operation.
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* We enable ONLY the pins we require to set. OMAP provides pins which do not
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* have alternate modes. Such pins done need to be set.
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*
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* See @ref MUX_VAL for description of the muxing mode.
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*
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* @return void
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*/
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static void mux_config(void)
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{
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/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
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/* D0-D7 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
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/* GPMC_NADV_ALE default mux mode is mode0 */
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/* GPMC_NOE default mux mode is mode0 */
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/* GPMC_NWE default mux mode is mode0 */
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/* GPMC_NBE0_CLE default mux mode is mode0 */
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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/* GPMC_WAIT0 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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/* SERIAL INTERFACE */
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
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/* I2C1_SCL default mux mode is mode0 */
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/* I2C1_SDA default mux mode is mode0 */
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/* USB EHCI (port 2) */
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MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
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/* Expansion card */
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */
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MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */
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MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */
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MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */
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MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */
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}
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/**
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* @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
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*
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* @return void
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*/
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static void sdrc_init(void)
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{
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/* SDRAM software reset */
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/* No idle ack and RESET enable */
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writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
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sdelay(100);
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/* No idle ack and RESET disable */
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writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
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/* SDRC Sharing register */
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/* 32-bit SDRAM on data lane [31:0] - CS0 */
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/* pin tri-stated = 1 */
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writel(0x00000100, OMAP3_SDRC_REG(SHARING));
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/* ----- SDRC Registers Configuration --------- */
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/* SDRC_MCFG0 register */
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writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
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/* SDRC_RFR_CTRL0 register */
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writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
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/* SDRC_ACTIM_CTRLA0 register */
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writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
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/* SDRC_ACTIM_CTRLB0 register */
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writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
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/* Disble Power Down of CKE due to 1 CKE on combo part */
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writel(0x00000081, OMAP3_SDRC_REG(POWER));
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/* SDRC_MANUAL command register */
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/* NOP command */
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writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
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/* Precharge command */
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writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
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/* SDRC MR0 register Burst length=4 */
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writel(0x00000032, OMAP3_SDRC_REG(MR_0));
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/* SDRC DLLA control register */
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writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
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return;
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static int beagle_board_init(void)
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{
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int in_sdram = omap3_running_in_sdram();
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if (!in_sdram)
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omap3_core_init();
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mux_config();
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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sdrc_init();
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return 0;
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}
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void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
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{
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omap3_save_bootinfo(data);
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arm_cpu_lowlevel_init();
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beagle_board_init();
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barebox_arm_entry(0x80000000, SZ_128M, NULL);
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}
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