139 lines
4.7 KiB
C
139 lines
4.7 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/imx25-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <io.h>
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#include <mach/imx-nand.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/sections.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/system.h>
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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uint32_t r;
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register uint32_t loops = 0x20000;
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arm_cpu_lowlevel_init();
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/* restart the MPLL and wait until it's stable */
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writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27),
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MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
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while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {};
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/* Configure dividers and ARM clock source
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* ARM @ 400 MHz
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* AHB @ 133 MHz
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*/
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writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
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/* Enable UART1 / FEC / */
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/* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0);
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writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1);
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writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2);*/
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, 0x43f00000);
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writel(0x77777777, 0x43f00004);
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writel(0x77777777, 0x53f00000);
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writel(0x77777777, 0x53f00004);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup
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* MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
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*/
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writel(0x00002143, 0x43f04000);
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writel(0x00002143, 0x43f04100);
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writel(0x00002143, 0x43f04200);
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writel(0x00002143, 0x43f04300);
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writel(0x00002143, 0x43f04400);
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/* SGPCR - always park on last master */
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writel(0x10, 0x43f04010);
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writel(0x10, 0x43f04110);
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writel(0x10, 0x43f04210);
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writel(0x10, 0x43f04310);
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writel(0x10, 0x43f04410);
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/* MGPCR - restore default values */
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writel(0x0, 0x43f04800);
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writel(0x0, 0x43f04900);
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writel(0x0, 0x43f04a00);
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writel(0x0, 0x43f04b00);
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writel(0x0, 0x43f04c00);
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/* Configure M3IF registers
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* M3IF Control Register (M3IFCTL) for MX25
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* MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
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* MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
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* MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
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* ----------
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* 0x00000001
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*/
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writel(0x1, 0xb8003000);
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/* Speed up NAND controller by adjusting the NFC divider */
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r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
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r &= ~0xf;
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r |= 0x1;
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writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0x90000000)
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goto out;
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/* Init Mobile DDR */
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writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400);
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writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX25_CSD0_BASE_ADDR);
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writeb(0xda, MX25_CSD0_BASE_ADDR);
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writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33);
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writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
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writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
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/* setup a stack to be able to call imx25_barebox_boot_nand_external() */
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arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12);
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imx25_barebox_boot_nand_external(0);
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}
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out:
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imx25_barebox_entry(NULL);
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}
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