113 lines
2.9 KiB
ArmAsm
113 lines
2.9 KiB
ArmAsm
/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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*/
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#include <config.h>
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#include <mach/imx27-regs.h>
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#include <asm/barebox-arm-head.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
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.macro sdram_init
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/*
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* DDR on CSD0
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*/
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writel(0x00000008, 0xD8001010)
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writel(0x55555555, 0x10027828)
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writel(0x55555555, 0x10027830)
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writel(0x55555555, 0x10027834)
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writel(0x00005005, 0x10027838)
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writel(0x15555555, 0x1002783C)
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2200000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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.endm
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.globl barebox_arm_reset_vector
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barebox_arm_reset_vector:
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bl arm_cpu_lowlevel_init
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/* ahb lite ip interface */
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writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
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writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
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writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
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writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
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/* disable mpll/spll */
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ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
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ldr r1, [r0]
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bic r1, r1, #0x03
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str r1, [r0]
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*
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* FIXME: Using the 399*2 MHz values from table 3-8 doens't work
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* with 1.2 V core voltage! Find out if this is
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* documented somewhere.
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*/
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writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */
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writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */
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/*
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* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
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* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
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* System clock (HCLK) = 133 MHz
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*/
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writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
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MX27_CCM_BASE_ADDR + MX27_CSCR)
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/* add some delay here */
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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/* clock gating enable */
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writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
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/* peripheral clock divider */
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/* FIXME */
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writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0)
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/* PERDIV1=08 @133 MHz */
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/* PERDIV1=04 @266 MHz */
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writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1)
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/* skip sdram initialization if we run from ram */
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cmp pc, #0xa0000000
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bls 1f
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cmp pc, #0xc0000000
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bhi 1f
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b imx27_barebox_entry
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1:
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sdram_init
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b imx27_barebox_entry
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