151 lines
4.6 KiB
C
151 lines
4.6 KiB
C
#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <mach/imx53-regs.h>
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#include <mach/imx5.h>
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#include <mach/iomux-v3.h>
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#include <mach/esdctl-v4.h>
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#include <mach/esdctl.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <io.h>
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#define IOMUX_PADCTL_DDRI_DDR (1 << 9)
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#define IOMUX_PADCTL_DDRDSE(x) ((x) << 19)
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#define IOMUX_PADCTL_DDRSEL(x) ((x) << 25)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x554
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x558
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x560
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x564
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x568
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x570
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x574
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x578
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x57c
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x580
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x588
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x590
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x594
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x584
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#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x6f0
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#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x6f4
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#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x6fc
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#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x710
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#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x714
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#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x718
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#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x71c
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#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x720
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#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x724
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#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x728
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#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x72c
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static void configure_dram_iomux(void)
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{
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void __iomem *iomux = (void *)MX53_IOMUXC_BASE_ADDR;
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u32 r1, r2, r4, r5, r6;
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/* define the INPUT mode for DRAM_D[31:0] */
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writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE);
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/*
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* define the INPUT mode for SDQS[3:0]
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* (Freescale's documentation suggests DDR-mode for the
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* control line, but their source actually uses CMOS)
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*/
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writel(IOMUX_PADCTL_DDRI_DDR, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL);
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r1 = IOMUX_PADCTL_DDRDSE(5);
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r2 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PUE;
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r4 = IOMUX_PADCTL_DDRSEL(2);
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r5 = IOMUX_PADCTL_DDRDSE(5) | PAD_CTL_PKE | PAD_CTL_PUE | IOMUX_PADCTL_DDRI_DDR | PAD_CTL_PUS_47K_UP;
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r6 = IOMUX_PADCTL_DDRDSE(4);
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/*
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* this will adisable the Pull/Keeper for DRAM_x pins EXCEPT,
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* for DRAM_SDQS[3:0] and DRAM_SDODT[1:0]
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*/
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writel(0, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRPKE);
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/* set global drive strength for all DRAM_x pins */
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writel(r4, iomux + IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE);
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/* set data dqs dqm drive strength */
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writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B0DS);
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writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0);
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writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B1DS);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1);
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writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1);
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writel(r6, iomux + IOMUXC_SW_PAD_CTL_GRP_B2DS);
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writel(r6, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2);
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writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_B3DS);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3);
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writel(r5, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3);
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/* SDCLK pad drive strength control options */
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1);
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/* Control and addr bus pad drive strength control options */
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_ADDDS);
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writel(r1, iomux + IOMUXC_SW_PAD_CTL_GRP_CTLDS);
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writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0);
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writel(r2, iomux + IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1);
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/*
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* enable hysteresis on input pins
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* (Freescale's documentation suggests that enable hysteresis
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* would be better, but their source-code doesn't)
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*/
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writel(PAD_CTL_HYS, iomux + IOMUXC_SW_PAD_CTL_GRP_DDRHYS);
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}
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void disable_watchdog(void)
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{
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/*
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* configure WDOG to generate external reset on trigger
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* and disable power down counter
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*/
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writew(0x38, MX53_WDOG1_BASE_ADDR);
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writew(0x0, MX53_WDOG1_BASE_ADDR + 8);
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writew(0x38, MX53_WDOG2_BASE_ADDR);
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writew(0x0, MX53_WDOG2_BASE_ADDR + 8);
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}
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void sdram_init(void);
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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u32 r;
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arm_cpu_lowlevel_init();
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x70000000 && r < 0xf0000000)
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imx53_barebox_entry(NULL);
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/* Setup a preliminary stack */
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r = 0xf8000000 + 0x60000 - 16;
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__asm__ __volatile__("mov sp, %0" : : "r"(r));
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disable_watchdog();
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configure_dram_iomux();
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imx5_init_lowlevel();
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imx_esdctlv4_init();
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imx53_barebox_entry(NULL);
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}
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