103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
/*
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* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* Under GPLv2
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/hardware.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91_wdt.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91sam9_smc.h>
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#include <mach/at91sam9_sdramc.h>
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#include <mach/at91sam9_matrix.h>
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#include <mach/at91_lowlevel_init.h>
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#define MASTER_PLL_DIV 15
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#define MASTER_PLL_MUL 162
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#define MAIN_PLL_DIV 2
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void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
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{
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/* Disable Watchdog */
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cfg->wdt_mr =
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AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
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AT91_WDT_WDV |
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AT91_WDT_WDDIS |
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AT91_WDT_WDD;
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/* define PDC[31:16] as DATA[31:16] */
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cfg->ebi_pio_pdr = 0xFFFF0000;
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/* no pull-up for D[31:16] */
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cfg->ebi_pio_ppudr = 0xFFFF0000;
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/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
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cfg->ebi_csa =
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AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
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cfg->smc_cs = 0;
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cfg->smc_mode =
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_DBW_16 |
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AT91_SMC_TDFMODE |
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AT91_SMC_TDF_(6);
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cfg->smc_cycle =
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AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
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cfg->smc_pulse =
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AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
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AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
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cfg->smc_setup =
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AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
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AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
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cfg->pmc_mor =
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AT91_PMC_MOSCEN |
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(255 << 8); /* Main Oscillator Start-up Time */
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cfg->pmc_pllar =
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AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
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AT91_PMC_OUT |
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
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/* PCK/2 = MCK Master Clock from PLLA */
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cfg->pmc_mckr1 =
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AT91_PMC_CSS_SLOW |
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AT91_PMC_PRES_1 |
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AT91SAM9_PMC_MDIV_2 |
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AT91_PMC_PDIV_1;
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/* PCK/2 = MCK Master Clock from PLLA */
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cfg->pmc_mckr2 =
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AT91_PMC_CSS_PLLA |
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AT91_PMC_PRES_1 |
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AT91SAM9_PMC_MDIV_2 |
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AT91_PMC_PDIV_1;
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/* SDRAM */
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/* SDRAMC_TR - Refresh Timer register */
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cfg->sdrc_tr1 = 0x13C;
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/* SDRAMC_CR - Configuration register*/
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cfg->sdrc_cr =
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AT91_SDRAMC_NC_9 |
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AT91_SDRAMC_NR_13 |
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AT91_SDRAMC_NB_4 |
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AT91_SDRAMC_CAS_3 |
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AT91_SDRAMC_DBW_32 |
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(1 << 8) | /* Write Recovery Delay */
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(7 << 12) | /* Row Cycle Delay */
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(3 << 16) | /* Row Precharge Delay */
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(2 << 20) | /* Row to Column Delay */
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(5 << 24) | /* Active to Precharge Delay */
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(1 << 28); /* Exit Self Refresh to Active Delay */
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/* Memory Device Register -> SDRAM */
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cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
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/* SDRAM_TR */
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cfg->sdrc_tr2 = 1200;
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/* user reset enable */
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cfg->rstc_rmr =
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AT91_RSTC_KEY |
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AT91_RSTC_PROCRST |
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AT91_RSTC_RSTTYP_WAKEUP |
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AT91_RSTC_RSTTYP_WATCHDOG;
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}
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