267 lines
6.5 KiB
C
267 lines
6.5 KiB
C
#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <mach/io.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#include <mach/cpu.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioDE_clk = {
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.name = "pioDE_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc0_clk = {
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.name = "mci0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb0_clk = {
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.name = "tcb0_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhphs_clk = {
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.name = "uhphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "macb_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc1_clk = {
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.name = "mci1_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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/* Video decoder clock - Only for sam9m10/sam9m11 */
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static struct clk vdec_clk = {
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.name = "vdec_clk",
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.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioDE_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc0_clk,
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&twi0_clk,
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&twi1_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tcb0_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&uhphs_clk,
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&lcdc_clk,
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&ac97_clk,
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&macb_clk,
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&isi_clk,
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&udphs_clk,
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&mmc1_clk,
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* One additional fake clock for ohci */
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CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
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CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
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CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
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CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
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CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
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CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
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CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
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CLKDEV_DEV_ID("at91-pit", &mck),
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CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9g45_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
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clk_register(&vdec_clk);
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clk_register(&pck0);
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clk_register(&pck1);
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}
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static void at91sam9g45_initialize(void)
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{
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/* Register the processor-specific clocks */
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at91sam9g45_register_clocks();
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/* Register GPIO subsystem */
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at91_add_rm9200_gpio(0, AT91SAM9G45_BASE_PIOA);
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at91_add_rm9200_gpio(1, AT91SAM9G45_BASE_PIOB);
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at91_add_rm9200_gpio(2, AT91SAM9G45_BASE_PIOC);
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at91_add_rm9200_gpio(3, AT91SAM9G45_BASE_PIOD);
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at91_add_rm9200_gpio(4, AT91SAM9G45_BASE_PIOE);
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at91_add_pit(AT91SAM9G45_BASE_PIT);
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at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
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}
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AT91_SOC_START(sam9g45)
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.init = at91sam9g45_initialize,
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AT91_SOC_END
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