193 lines
6.6 KiB
C
193 lines
6.6 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx21-regs.h>
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#include "clk.h"
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/* Register offsets */
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#define CCM_CSCR 0x0
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#define CCM_MPCTL0 0x4
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#define CCM_MPCTL1 0x8
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#define CCM_SPCTL0 0xc
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#define CCM_SPCTL1 0x10
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#define CCM_OSC26MCTL 0x14
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#define CCM_PCDR0 0x18
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#define CCM_PCDR1 0x1c
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#define CCM_PCCR0 0x20
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#define CCM_PCCR1 0x24
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#define CCM_CCSR 0x28
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#define CCM_PMCTL 0x2c
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#define CCM_PMCOUNT 0x30
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#define CCM_WKGDCTL 0x34
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#define PCCR0_UART1_EN (1 << 0)
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#define PCCR0_UART2_EN (1 << 1)
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#define PCCR0_UART3_EN (1 << 2)
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#define PCCR0_UART4_EN (1 << 3)
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#define PCCR0_CSPI1_EN (1 << 4)
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#define PCCR0_CSPI2_EN (1 << 5)
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#define PCCR0_SSI1_EN (1 << 6)
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#define PCCR0_SSI2_EN (1 << 7)
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#define PCCR0_FIRI_EN (1 << 8)
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#define PCCR0_SDHC1_EN (1 << 9)
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#define PCCR0_SDHC2_EN (1 << 10)
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#define PCCR0_GPIO_EN (1 << 11)
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#define PCCR0_I2C_EN (1 << 12)
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#define PCCR0_DMA_EN (1 << 13)
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#define PCCR0_USBOTG_EN (1 << 14)
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#define PCCR0_EMMA_EN (1 << 15)
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#define PCCR0_SSI2_BAUD_EN (1 << 16)
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#define PCCR0_SSI1_BAUD_EN (1 << 17)
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#define PCCR0_PERCLK3_EN (1 << 18)
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#define PCCR0_NFC_EN (1 << 19)
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#define PCCR0_FRI_BAUD_EN (1 << 20)
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#define PCCR0_SLDC_EN (1 << 21)
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#define PCCR0_PERCLK4_EN (1 << 22)
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#define PCCR0_HCLK_BMI_EN (1 << 23)
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#define PCCR0_HCLK_USBOTG_EN (1 << 24)
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#define PCCR0_HCLK_SLCDC_EN (1 << 25)
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#define PCCR0_HCLK_LCDC_EN (1 << 26)
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#define PCCR0_HCLK_EMMA_EN (1 << 27)
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#define PCCR0_HCLK_BROM_EN (1 << 28)
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#define PCCR0_HCLK_DMA_EN (1 << 30)
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#define PCCR0_HCLK_CSI_EN (1 << 31)
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#define PCCR1_CSPI3_EN (1 << 23)
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#define PCCR1_WDT_EN (1 << 24)
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#define PCCR1_GPT1_EN (1 << 25)
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#define PCCR1_GPT2_EN (1 << 26)
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#define PCCR1_GPT3_EN (1 << 27)
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#define PCCR1_PWM_EN (1 << 28)
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#define PCCR1_RTC_EN (1 << 29)
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#define PCCR1_KPP_EN (1 << 30)
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#define PCCR1_OWIRE_EN (1 << 31)
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enum imx21_clks {
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ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
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per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, lcdc_ahb_gate,
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lcdc_ipg_gate, clk_max
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};
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static struct clk *clks[clk_max];
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static const char *mpll_sel_clks[] = {
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"fpm",
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"ckih",
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};
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static const char *spll_sel_clks[] = {
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"fpm",
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"ckih",
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};
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static int imx21_ccm_probe(struct device_d *dev)
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{
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void __iomem *base;
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unsigned long lref = 32768;
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unsigned long href = 26000000;
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base = dev_request_mem_region(dev, 0);
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writel(PCCR0_UART1_EN | PCCR0_UART2_EN | PCCR0_UART3_EN | PCCR0_UART4_EN |
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PCCR0_CSPI1_EN | PCCR0_CSPI2_EN | PCCR0_SDHC1_EN |
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PCCR0_SDHC2_EN | PCCR0_GPIO_EN | PCCR0_I2C_EN | PCCR0_DMA_EN |
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PCCR0_USBOTG_EN | PCCR0_NFC_EN | PCCR0_PERCLK4_EN |
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PCCR0_HCLK_USBOTG_EN | PCCR0_HCLK_DMA_EN,
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base + CCM_PCCR0);
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writel(PCCR1_CSPI3_EN | PCCR1_WDT_EN | PCCR1_GPT1_EN | PCCR1_GPT2_EN |
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PCCR1_GPT3_EN | PCCR1_PWM_EN | PCCR1_RTC_EN | PCCR1_KPP_EN |
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PCCR1_OWIRE_EN,
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base + CCM_PCCR1);
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clks[ckil] = clk_fixed("ckil", lref);
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clks[ckih] = clk_fixed("ckih", href);
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clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
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clks[mpll_sel] = imx_clk_mux("mpll_sel", base + CCM_CSCR, 16, 1, mpll_sel_clks,
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ARRAY_SIZE(mpll_sel_clks));
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clks[spll_sel] = imx_clk_mux("spll_sel", base + CCM_CSCR, 17, 1, spll_sel_clks,
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ARRAY_SIZE(spll_sel_clks));
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clks[mpll] = imx_clk_pllv1("mpll", "mpll_sel", base + CCM_MPCTL0);
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clks[spll] = imx_clk_pllv1("spll", "spll_sel", base + CCM_SPCTL0);
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clks[fclk] = imx_clk_divider("fclk", "mpll", base + CCM_CSCR, 29, 3);
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clks[hclk] = imx_clk_divider("hclk", "fclk", base + CCM_CSCR, 10, 4);
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clks[ipg] = imx_clk_divider("ipg", "hclk", base + CCM_CSCR, 9, 1);
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clks[per1] = imx_clk_divider("per1", "mpll", base + CCM_PCDR1, 0, 6);
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clks[per2] = imx_clk_divider("per2", "mpll", base + CCM_PCDR1, 8, 6);
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clks[per3] = imx_clk_divider("per3", "mpll", base + CCM_PCDR1, 16, 6);
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clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6);
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clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3);
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clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4);
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clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18);
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clks[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", base + CCM_PCCR0, 26);
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/*
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* i.MX21 doesn't have an IPG clock for the LCD. To avoid even more conditionals
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* in the framebuffer code, provide a dummy clock.
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*/
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clks[lcdc_ipg_gate] = clk_fixed("dummy", 0);
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clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_GPT3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_UART3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX21_CSPI3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, "per");
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clkdev_add_physbase(clks[lcdc_ahb_gate], MX21_LCDC_BASE_ADDR, "ahb");
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clkdev_add_physbase(clks[lcdc_ipg_gate], MX21_LCDC_BASE_ADDR, "ipg");
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return 0;
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}
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static __maybe_unused struct of_device_id imx21_ccm_dt_ids[] = {
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{
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.compatible = "fsl,imx21-ccm",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx21_ccm_driver = {
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.probe = imx21_ccm_probe,
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.name = "imx21-ccm",
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.of_compatible = DRV_OF_COMPAT(imx21_ccm_dt_ids),
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};
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static int imx21_ccm_init(void)
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{
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return platform_driver_register(&imx21_ccm_driver);
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}
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core_initcall(imx21_ccm_init);
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