324 lines
13 KiB
C
324 lines
13 KiB
C
/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-silicon.h>
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#define MUX_CFG(value, offset) \
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__raw_writel(value, (AM33XX_CTRL_BASE + offset));
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static const __maybe_unused struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux uart2_pin_mux[] = {
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{OFFSET(mii1_txclk), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART2_RXD */
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{OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
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{OFFSET(spi0_cs1), (MODE(1) | PULLUDEN | RXACTIVE)}, /* UART3_RXD */
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{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux i2c1_pin_mux[] = {
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{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux i2c2_pin_mux[] = {
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{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
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{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux rgmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
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{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
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{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
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{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
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{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
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{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
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{OFFSET(gpmc_a6), MODE(2)}, /* RGMII2_TCLK */
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{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
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{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
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{OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII2_RD2 */
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{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
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{OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII2_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux rmii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
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{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
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{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux rmii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
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{OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
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{OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
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{OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
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{OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
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{OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRS */
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{OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXERR */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_REFCLK */
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{-1},
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};
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#ifdef CONFIG_NOR
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static const __maybe_unused struct module_pin_mux nor_pin_mux[] = {
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{OFFSET(lcd_data0), MODE(1) | PULLUDEN}, /* NOR_A0 */
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{OFFSET(lcd_data1), MODE(1) | PULLUDEN}, /* NOR_A1 */
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{OFFSET(lcd_data2), MODE(1) | PULLUDEN}, /* NOR_A2 */
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{OFFSET(lcd_data3), MODE(1) | PULLUDEN}, /* NOR_A3 */
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{OFFSET(lcd_data4), MODE(1) | PULLUDEN}, /* NOR_A4 */
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{OFFSET(lcd_data5), MODE(1) | PULLUDEN}, /* NOR_A5 */
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{OFFSET(lcd_data6), MODE(1) | PULLUDEN}, /* NOR_A6 */
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{OFFSET(lcd_data7), MODE(1) | PULLUDEN}, /* NOR_A7 */
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{OFFSET(gpmc_a8), MODE(0)}, /* NOR_A8 */
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{OFFSET(gpmc_a9), MODE(0)}, /* NOR_A9 */
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{OFFSET(gpmc_a10), MODE(0)}, /* NOR_A10 */
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{OFFSET(gpmc_a11), MODE(0)}, /* NOR_A11 */
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{OFFSET(lcd_data8), MODE(1) | PULLUDEN}, /* NOR_A12 */
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{OFFSET(lcd_data9), MODE(1) | PULLUDEN}, /* NOR_A13 */
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{OFFSET(lcd_data10), MODE(1) | PULLUDEN}, /* NOR_A14 */
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{OFFSET(lcd_data11), MODE(1) | PULLUDEN}, /* NOR_A15 */
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{OFFSET(lcd_data12), MODE(1) | PULLUDEN}, /* NOR_A16 */
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{OFFSET(lcd_data13), MODE(1) | PULLUDEN}, /* NOR_A17 */
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{OFFSET(lcd_data14), MODE(1) | PULLUDEN}, /* NOR_A18 */
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{OFFSET(lcd_data15), MODE(1) | PULLUDEN}, /* NOR_A19 */
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{OFFSET(gpmc_a4), MODE(4)}, /* NOR_A20 */
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{OFFSET(gpmc_a5), MODE(4)}, /* NOR_A21 */
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{OFFSET(gpmc_a6), MODE(4)}, /* NOR_A22 */
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{OFFSET(gpmc_ad0), MODE(0) | RXACTIVE}, /* NOR_AD0 */
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{OFFSET(gpmc_ad1), MODE(0) | RXACTIVE}, /* NOR_AD1 */
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{OFFSET(gpmc_ad2), MODE(0) | RXACTIVE}, /* NOR_AD2 */
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{OFFSET(gpmc_ad3), MODE(0) | RXACTIVE}, /* NOR_AD3 */
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{OFFSET(gpmc_ad4), MODE(0) | RXACTIVE}, /* NOR_AD4 */
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{OFFSET(gpmc_ad5), MODE(0) | RXACTIVE}, /* NOR_AD5 */
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{OFFSET(gpmc_ad6), MODE(0) | RXACTIVE}, /* NOR_AD6 */
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{OFFSET(gpmc_ad7), MODE(0) | RXACTIVE}, /* NOR_AD7 */
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{OFFSET(gpmc_ad8), MODE(0) | RXACTIVE}, /* NOR_AD8 */
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{OFFSET(gpmc_ad9), MODE(0) | RXACTIVE}, /* NOR_AD9 */
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{OFFSET(gpmc_ad10), MODE(0) | RXACTIVE}, /* NOR_AD10 */
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{OFFSET(gpmc_ad11), MODE(0) | RXACTIVE}, /* NOR_AD11 */
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{OFFSET(gpmc_ad12), MODE(0) | RXACTIVE}, /* NOR_AD12 */
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{OFFSET(gpmc_ad13), MODE(0) | RXACTIVE}, /* NOR_AD13 */
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{OFFSET(gpmc_ad14), MODE(0) | RXACTIVE}, /* NOR_AD14 */
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{OFFSET(gpmc_ad15), MODE(0) | RXACTIVE}, /* NOR_AD15 */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* NOR_CE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, /* NOR_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, /* NOR_WEN */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NOR WAIT */
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{OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDEN}, /* NOR RESET */
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{-1},
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};
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#endif
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static const __maybe_unused struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(uart1_rxd), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(mcasp0_fsx), (MODE(4) | RXACTIVE)}, /* MMC1_CD */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux spi0_pin_mux[] = {
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{OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
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{OFFSET(spi0_d0), MODE(0) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI0_D0 */
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{OFFSET(spi0_d1), MODE(0) | PULLUDEN |
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RXACTIVE}, /*SPI0_D1 */
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{OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /*SPI0_CS0 */
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{-1},
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};
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static const __maybe_unused struct module_pin_mux spi1_pin_mux[] = {
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{OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_SCLK */
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{OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI0_D0 */
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{OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, /*SPI0_D1 */
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{OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN |
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RXACTIVE}, /*SPI0_CS0 */
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{-1},
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};
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/*
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* Configure the pin mux for the module
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*/
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void configure_module_pin_mux(const struct module_pin_mux *mod_pin_mux)
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{
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int i;
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if (!mod_pin_mux)
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return;
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for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
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MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
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}
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void am33xx_enable_mii1_pin_mux(void)
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{
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configure_module_pin_mux(mii1_pin_mux);
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}
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void am33xx_enable_rmii1_pin_mux(void)
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{
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configure_module_pin_mux(rmii1_pin_mux);
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}
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void am33xx_enable_rmii2_pin_mux(void)
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{
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configure_module_pin_mux(rmii2_pin_mux);
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}
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void am33xx_enable_i2c0_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void am33xx_enable_i2c1_pin_mux(void)
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{
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configure_module_pin_mux(i2c1_pin_mux);
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}
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void am33xx_enable_i2c2_pin_mux(void)
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{
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configure_module_pin_mux(i2c2_pin_mux);
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}
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void am33xx_enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void am33xx_enable_uart2_pin_mux(void)
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{
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configure_module_pin_mux(uart2_pin_mux);
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}
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void am33xx_enable_mmc0_pin_mux(void)
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{
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configure_module_pin_mux(mmc0_pin_mux);
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}
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void am33xx_enable_spi0_pin_mux(void)
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{
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configure_module_pin_mux(spi0_pin_mux);
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}
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void am33xx_enable_nand_pin_mux(void)
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{
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configure_module_pin_mux(nand_pin_mux);
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}
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