541 lines
12 KiB
C
541 lines
12 KiB
C
/**
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* @file
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* @brief Provide Generic implementations for OMAP3 architecture
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*
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* This file contains the generic implementations of various OMAP3
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* relevant functions
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* For more info on OMAP34XX, see http://focus.ti.com/pdfs/wtbu/swpu114g.pdf
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*
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* Important one is @ref a_init which is architecture init code.
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* The implemented functions are present in sys_info.h
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*
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* Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
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*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <bootsource.h>
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#include <init.h>
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#include <io.h>
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#include <mach/omap3-silicon.h>
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#include <mach/gpmc.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/control.h>
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#include <mach/omap3-smx.h>
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#include <mach/clocks.h>
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#include <mach/omap3-clock.h>
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#include <mach/wdt.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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/**
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* @brief Reset the CPU
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*
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* In case of crashes, reset the CPU
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*
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* @param addr Cause of crash
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*
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* @return void
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*/
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void __noreturn omap3_reset_cpu(unsigned long addr)
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{
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writel(OMAP3_PRM_RSTCTRL_RESET, OMAP3_PRM_REG(RSTCTRL));
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while (1);
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}
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EXPORT_SYMBOL(reset_cpu);
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/**
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* @brief Low level CPU type
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*
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* @return Detected CPU type
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*/
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u32 get_cpu_type(void)
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{
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u32 idcode_val;
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u16 hawkeye;
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idcode_val = readl(OMAP3_IDCODE_REG);
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hawkeye = get_hawkeye(idcode_val);
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if (hawkeye == OMAP_HAWKEYE_34XX)
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return CPU_3430;
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if (hawkeye == OMAP_HAWKEYE_36XX)
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return CPU_3630;
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/*
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* Fallback to OMAP3430 as default.
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*/
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return CPU_3430;
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}
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/**
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* @brief Extract the OMAP ES revision
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*
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* The significance of the CPU revision depends upon the cpu type.
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* Latest known revision is considered default.
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*
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* @return silicon version
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*/
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u32 get_cpu_rev(void)
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{
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u32 idcode_val;
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u32 version, retval;
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idcode_val = readl(OMAP3_IDCODE_REG);
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version = get_version(idcode_val);
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switch (get_cpu_type()) {
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case CPU_3630:
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switch (version) {
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case 0:
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retval = OMAP36XX_ES1;
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break;
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case 1:
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retval = OMAP36XX_ES1_1;
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break;
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case 2:
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/*
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* Fall through the default case.
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*/
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default:
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retval = OMAP36XX_ES1_2;
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}
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break;
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case CPU_3430:
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/*
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* Same as default case
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*/
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default:
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/*
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* On OMAP3430 ES1.0 the IDCODE register is not exposed on L4.
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* Use CPU ID to check for the same.
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*/
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__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(retval));
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if ((retval & 0xf) == 0x0) {
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retval = OMAP34XX_ES1;
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} else {
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switch (version) {
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case 0: /* This field was not set in early samples */
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case 1:
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retval = OMAP34XX_ES2;
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break;
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case 2:
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retval = OMAP34XX_ES2_1;
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break;
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case 3:
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retval = OMAP34XX_ES3;
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break;
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case 4:
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/*
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* Same as default case
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*/
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default:
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retval = OMAP34XX_ES3_1;
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}
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}
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}
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return retval;
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}
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/**
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* @brief Get size of chip select 0/1
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*
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* @param[in] offset give the offset if we need CS1
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*
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* @return return the sdram size.
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*/
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u32 get_sdr_cs_size(u32 offset)
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{
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u32 size;
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/* get ram size field */
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size = readl(OMAP3_SDRC_REG(MCFG_0) + offset) >> 8;
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size &= 0x3FF; /* remove unwanted bits */
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size *= 2 * (1024 * 1024); /* find size in MB */
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return size;
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}
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EXPORT_SYMBOL(get_sdr_cs_size);
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/**
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* @brief base address of chip select 1 (cs0 is defined at 0x80000000)
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*
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* @return return the CS1 base address.
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*/
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u32 get_sdr_cs1_base(void)
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{
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u32 base;
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u32 cs_cfg;
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cs_cfg = readl(OMAP3_SDRC_REG(CS_CFG));
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/* get ram size field */
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base = (cs_cfg & 0x0000000F) << 2; /* get CS1STARTHIGH */
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base = base | ((cs_cfg & 0x00000300) >> 8); /* get CS1STARTLOW */
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base = base << 25;
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base += 0x80000000;
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return base;
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}
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EXPORT_SYMBOL(get_sdr_cs1_base);
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/**
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* @brief Get the initial SYSBOOT value
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*
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* SYSBOOT is useful to know which state OMAP booted from.
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*
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* @return - Return the value of SYSBOOT.
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*/
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inline u32 get_sysboot_value(void)
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{
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return (0x0000003F & readl(OMAP3_CONTROL_REG(STATUS)));
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}
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/**
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* @brief Get the upper address of current execution
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*
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* we can use this to figure out if we are running in SRAM /
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* XIP Flash or in SDRAM
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*
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* @return base address
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*/
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static u32 get_base(void)
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{
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u32 val;
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__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
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val &= 0xF0000000;
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val >>= 28;
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return val;
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}
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/**
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* @brief Are we running in Flash XIP?
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*
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* If the base is in GPMC address space, we probably are!
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*
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* @return 1 if we are running in XIP mode, else return 0
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*/
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u32 omap3_running_in_flash(void)
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{
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if (get_base() < 4)
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return 1; /* in flash */
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return 0; /* running in SRAM or SDRAM */
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}
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/**
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* @brief Are we running in OMAP internal SRAM?
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*
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* If in SRAM address, then yes!
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*
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* @return 1 if we are running in SRAM, else return 0
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*/
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u32 omap3_running_in_sram(void)
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{
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if (get_base() == 4)
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return 1; /* in SRAM */
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return 0; /* running in FLASH or SDRAM */
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}
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/**
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* @brief Are we running in SDRAM?
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*
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* if we are not in GPMC nor in SRAM address space,
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* we are in SDRAM execution area
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*
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* @return 1 if we are running from SDRAM, else return 0
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*/
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u32 omap3_running_in_sdram(void)
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{
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if (get_base() > 4)
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return 1; /* in sdram */
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return 0; /* running in SRAM or FLASH */
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}
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EXPORT_SYMBOL(omap3_running_in_sdram);
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/**
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* @brief Is this an XIP type device or a stream one
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*
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* Sysboot bits 4-0 specify type. Bit 5, sys mem/perif
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*
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* @return Boot type
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*/
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u32 get_boot_type(void)
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{
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u32 v;
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v = get_sysboot_value() & ((0x1 << 4) | (0x1 << 3) | (0x1 << 2) |
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(0x1 << 1) | (0x1 << 0));
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return v;
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}
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/**
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* @brief What type of device are we?
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*
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* are we on a GP/HS/EMU/TEST device?
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*
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* @return device type
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*/
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u32 get_device_type(void)
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{
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int mode;
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mode = readl(OMAP3_CONTROL_REG(STATUS)) & (DEVICE_MASK);
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return (mode >>= 8);
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}
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/**
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* @brief Setup security registers for access
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*
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* This can be done for GP Device only. for HS/EMU devices, read TRM.
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*
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* @return void
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*/
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static void secure_unlock_mem(void)
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{
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/* Permission values for registers -Full fledged permissions to all */
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#define UNLOCK_1 0xFFFFFFFF
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#define UNLOCK_2 0x00000000
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#define UNLOCK_3 0x0000FFFF
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/* Protection Module Register Target APE (PM_RT) */
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writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
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writel(UNLOCK_1, RT_READ_PERMISSION_0);
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writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
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writel(UNLOCK_2, RT_ADDR_MATCH_1);
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writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
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writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
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writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, OCM_READ_PERMISSION_0);
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writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
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writel(UNLOCK_2, OCM_ADDR_MATCH_2);
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/* IVA Changes */
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writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
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writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
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writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
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writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
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}
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/**
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* @brief Come out of secure mode
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* If chip is EMU and boot type is external configure
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* secure registers and exit secure world general use.
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*
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* @return void
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*/
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static void secureworld_exit(void)
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{
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unsigned long i;
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/* configrue non-secure access control register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
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/* enabling co-processor CP10 and CP11 accesses in NS world */
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__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
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/* allow allocation of locked TLBs and L2 lines in NS world */
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/* allow use of PLE registers in NS world also */
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__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
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/* Enable ASA in ACR register */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
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/* Exiting secure world */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
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__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
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__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
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}
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/**
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* @brief Shut down the watchdogs
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*
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* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
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* either taken care of by ROM (HS/EMU) or not accessible (GP).
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* We need to take care of WD2-MPU or take a PRCM reset. WD3
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* should not be running and does not generate a PRCM reset.
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*
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* @return void
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*/
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static void watchdog_init(void)
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{
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int pending = 1;
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sr32(OMAP3_CM_REG(FCLKEN_WKUP), 5, 1, 1);
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sr32(OMAP3_CM_REG(ICLKEN_WKUP), 5, 1, 1);
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wait_on_value((0x1 << 5), 0x20, OMAP3_CM_REG(IDLEST_WKUP), 5);
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writel(WDT_DISABLE_CODE1, OMAP3_WDT_REG(WSPR));
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do {
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pending = readl(OMAP3_WDT_REG(WWPS));
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} while (pending);
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writel(WDT_DISABLE_CODE2, OMAP3_WDT_REG(WSPR));
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}
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/**
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* @brief Write to AuxCR desired value using SMI.
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* general use.
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*
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* @return void
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*/
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void setup_auxcr(void);
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/**
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* @brief Try to unlock the SRAM for general use
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*
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* If chip is GP/EMU(special) type, unlock the SRAM for
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* general use.
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*
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* @return void
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*/
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static void try_unlock_memory(void)
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{
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int mode;
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int in_sdram = omap3_running_in_sdram();
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/* if GP device unlock device SRAM for general use */
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/* secure code breaks for Secure/Emulation device - HS/E/T */
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mode = get_device_type();
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if (mode == GP_DEVICE)
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secure_unlock_mem();
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/* If device is EMU and boot is XIP external booting
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* Unlock firewalls and disable L2 and put chip
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* out of secure world
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*/
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/* Assuming memories are unlocked by the demon who put us in SDRAM */
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if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
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&& (!in_sdram)) {
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secure_unlock_mem();
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secureworld_exit();
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}
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return;
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}
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/**
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* @brief OMAP3 Architecture specific Initialization
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*
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* Does early system init of disabling the watchdog, enable
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* memory and configuring the clocks.
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*
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* prcm_init is called only if CONFIG_OMAP3_CLOCK_CONFIG is defined.
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* We depend on link time clean up to remove a_init if no caller exists.
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*
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* @warning Called path is with SRAM stack
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*
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* @return void
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*/
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void omap3_core_init(void)
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{
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watchdog_init();
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try_unlock_memory();
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/* Writing to AuxCR in barebox using SMI for GP DEV */
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/* Currently SMI in Kernel on ES2 devices seems to have an isse
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* Once that is resolved, we can postpone this config to kernel
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*/
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if (get_device_type() == GP_DEVICE) {
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setup_auxcr();
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omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
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}
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sdelay(100);
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#ifdef CONFIG_OMAP3_CLOCK_CONFIG
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prcm_init();
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#endif
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}
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#define OMAP3_TRACING_VECTOR1 0x4020ffb4
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static int omap3_bootsource(void)
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{
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enum bootsource src = BOOTSOURCE_UNKNOWN;
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uint32_t *omap3_bootinfo = (void *)OMAP3_SRAM_SCRATCH_SPACE;
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switch (omap3_bootinfo[1] & 0xFF) {
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case 0x02:
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src = BOOTSOURCE_NAND;
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break;
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case 0x06:
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src = BOOTSOURCE_MMC;
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break;
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case 0x11:
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src = BOOTSOURCE_USB;
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break;
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default:
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src = BOOTSOURCE_UNKNOWN;
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}
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bootsource_set(src);
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bootsource_set_instance(0);
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return 0;
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}
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int omap3_init(void)
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{
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omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
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return omap3_bootsource();
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}
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|
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/* GPMC timing for OMAP3 nand device */
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const struct gpmc_config omap3_nand_cfg = {
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.cfg = {
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0x00000000, /* CONF1 */
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0x00141400, /* CONF2 */
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0x00141400, /* CONF3 */
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0x0F010F01, /* CONF4 */
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0x010C1414, /* CONF5 */
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0x1F040000 |
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0x00000A80, /* CONF6 */
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},
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/* GPMC address map as small as possible */
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.base = 0x28000000,
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.size = GPMC_SIZE_16M,
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};
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|
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#ifndef __PBL__
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static int omap3_gpio_init(void)
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{
|
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add_generic_device("omap-gpio", 0, NULL, OMAP3_GPIO1_BASE,
|
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 1, NULL, OMAP3_GPIO2_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 2, NULL, OMAP3_GPIO3_BASE,
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0xf00, IORESOURCE_MEM, NULL);
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add_generic_device("omap-gpio", 3, NULL, OMAP3_GPIO4_BASE,
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0xf00, IORESOURCE_MEM, NULL);
|
|
add_generic_device("omap-gpio", 4, NULL, OMAP3_GPIO5_BASE,
|
|
0xf00, IORESOURCE_MEM, NULL);
|
|
add_generic_device("omap-gpio", 5, NULL, OMAP3_GPIO6_BASE,
|
|
0xf00, IORESOURCE_MEM, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int omap3_devices_init(void)
|
|
{
|
|
return omap3_gpio_init();
|
|
}
|
|
#endif
|