303 lines
7.3 KiB
C
303 lines
7.3 KiB
C
/*
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* Copyright (C) 2012 Juergen Beisert
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*
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* This code bases partially on code from the Linux kernel:
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <io.h>
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#include <gpio.h>
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#include <mach/iomux.h>
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#include <mach/s3c-iomap.h>
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#define S3C_GPACON (S3C_GPIO_BASE)
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#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
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#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
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static const unsigned short group_offset[] = {
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0x000, /* GPA */ /* 8 pins, 4 bit each */
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0x020, /* GPB */ /* 7 pins, 4 bit each */
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0x040, /* GPC */ /* 8 pins, 4 bit each */
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0x060, /* GPD */ /* 5 pins, 4 bit each */
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0x080, /* GPE */ /* 5 pins, 4 bit each */
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0x0a0, /* GPF */ /* 16 pins, 2 bit each */
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0x0c0, /* GPG */ /* 7 pins, 4 bit each */
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0x0e0, /* GPH */ /* two registers, 8 + 2 pins, 4 bit each */
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0x100, /* GPI */ /* 16 pins, 2 bit each */
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0x120, /* GPJ */ /* 12 pins, 2 bit each */
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0x800, /* GPK */ /* two registers, 8 + 8 pins, 4 bit each */
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0x810, /* GPL */ /* two registers, 8 + 8 pins, 4 bit each */
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0x820, /* GPM */ /* 6 pins, 4 bit each */
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0x830, /* GPN */ /* 16 pins, 2 bit each */
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0x140, /* GPO */ /* 16 pins, 2 bit each */
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0x160, /* GPP */ /* 15 pins, 2 bit each */
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0x180, /* GPQ */ /* 9 pins, 2 bit each */
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};
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void gpio_set_value(unsigned gpio, int value)
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{
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unsigned group = GET_GROUP(gpio);
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unsigned bit = GET_BIT(gpio);
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unsigned offset;
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uint32_t reg;
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offset = group_offset[group];
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switch (group) {
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case 7: /* GPH */
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case 10: /* GPK */
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case 11: /* GPL */
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offset += 4;
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break;
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}
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reg = readl(S3C_GPADAT + offset);
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reg &= ~(1 << bit);
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reg |= (!!value) << bit;
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writel(reg, S3C_GPADAT + offset);
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}
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int gpio_get_value(unsigned gpio)
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{
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unsigned group = GET_GROUP(gpio);
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unsigned bit = GET_BIT(gpio);
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unsigned offset;
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uint32_t reg;
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offset = group_offset[group];
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switch (group) {
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case 7: /* GPH */
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case 10: /* GPK */
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case 11: /* GPL */
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offset += 4;
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break;
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}
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/* value */
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reg = readl(S3C_GPADAT + offset);
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return !!(reg & (1 << bit));
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}
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static void gpio_direction_input_4b(unsigned offset, unsigned bit)
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{
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uint32_t reg;
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if (bit > 31) {
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offset += 4;
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bit -= 32;
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}
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reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
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writel(reg, S3C_GPACON + offset); /* b0000 means 'GPIO input' */
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}
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static void gpio_direction_input_2b(unsigned offset, unsigned bit)
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{
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uint32_t reg;
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reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
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writel(reg, S3C_GPACON + offset); /* b00 means 'GPIO input' */
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}
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int gpio_direction_input(unsigned gpio)
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{
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unsigned group = GET_GROUP(gpio);
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unsigned bit = GET_BIT(gpio);
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unsigned offset;
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offset = group_offset[group];
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switch (group) {
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case 5: /* GPF */
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case 8: /* GPI */
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case 9: /* GPJ */
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case 13: /* GPN */
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case 14: /* GPO */
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case 15: /* GPP */
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case 16: /* GPQ */
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gpio_direction_input_2b(offset, bit << 1);
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break;
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default:
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gpio_direction_input_4b(offset, bit << 2);
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}
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return 0;
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}
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static void gpio_direction_output_4b(unsigned offset, unsigned bit)
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{
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uint32_t reg;
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if (bit > 31) {
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offset += 4;
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bit -= 32;
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}
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reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
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reg |= 0x1 << bit;
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writel(reg, S3C_GPACON + offset); /* b0001 means 'GPIO output' */
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}
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static void gpio_direction_output_2b(unsigned offset, unsigned bit)
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{
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uint32_t reg;
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/* direction */
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reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
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reg |= 0x1 << bit;
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writel(reg, S3C_GPACON + offset);
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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unsigned group = GET_GROUP(gpio);
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unsigned bit = GET_BIT(gpio);
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unsigned offset;
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gpio_set_value(gpio, value);
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offset = group_offset[group];
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switch (group) {
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case 5: /* GPF */
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case 8: /* GPI */
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case 9: /* GPJ */
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case 13: /* GPN */
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case 14: /* GPO */
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case 15: /* GPP */
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case 16: /* GPQ */
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gpio_direction_output_2b(offset, bit << 1);
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break;
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default:
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gpio_direction_output_4b(offset, bit << 2);
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}
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return 0;
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}
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/* one register, 2 bits per function -> GPF, GPI, GPJ, GPN, GPO, GPP, GPQ */
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static void s3c_d2pins(unsigned offset, unsigned pin_mode)
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{
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unsigned bit = GET_BIT(pin_mode);
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unsigned func = GET_FUNC(pin_mode);
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unsigned reg;
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if (PUD_PRESENT(pin_mode)) {
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reg = readl(S3C_GPAPUD + offset);
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reg &= ~(PUD_MASK << bit);
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reg |= GET_PUD(pin_mode) << bit;
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writel(reg, S3C_GPAPUD + offset);
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}
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/* in the case of pin's function is GPIO it also sets up the direction */
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reg = readl(S3C_GPACON + offset) & ~(0x3 << bit);
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writel(reg | (func << bit), S3C_GPACON + offset);
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if (func == 1) { /* output? if yes, also set the initial value */
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reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 1));
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reg |= GET_GPIOVAL(pin_mode) << (bit >> 1);
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writel(reg, S3C_GPADAT + offset);
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}
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}
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/* one register, 4 bits per function -> GPA, GPB, GPC, GPD, GPE, GPG, GPM */
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static void s3c_d4pins(unsigned offset, unsigned pin_mode)
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{
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unsigned bit = GET_BIT(pin_mode);
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unsigned func = GET_FUNC(pin_mode);
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unsigned reg;
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if (PUD_PRESENT(pin_mode)) {
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reg = readl(S3C_GPAPUD + offset);
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reg &= ~(PUD_MASK << (bit >> 1));
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reg |= GET_PUD(pin_mode) << (bit >> 1);
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writel(reg, S3C_GPAPUD + offset);
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}
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/* in the case of pin's function is GPIO it also sets up the direction */
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reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
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writel(reg | (func << bit), S3C_GPACON + offset);
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if (func == 1) { /* output? if yes, also set the initial value */
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reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
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reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
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writel(reg, S3C_GPADAT + offset);
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}
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}
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/* two registers, 4 bits per pin -> GPH, GPK, GPL */
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static void s3c_d42pins(unsigned offset, unsigned pin_mode)
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{
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unsigned bit = GET_BIT(pin_mode);
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unsigned func = GET_FUNC(pin_mode);
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uint32_t reg;
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unsigned reg_offs = 0;
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if (PUD_PRESENT(pin_mode)) {
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reg = readl(S3C_GPAPUD + 4 + offset);
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reg &= ~(PUD_MASK << (bit >> 1));
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reg |= GET_PUD(pin_mode) << (bit >> 1);
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writel(reg, S3C_GPACON + 4 + offset);
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}
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if (bit > 31) {
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reg_offs = 4;
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bit -= 32;
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}
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/* in the case of pin's function is GPIO it also sets up the direction */
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reg = readl(S3C_GPACON + offset + reg_offs) & ~(0xf << bit);
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writel(reg | (func << bit), S3C_GPACON + offset + reg_offs);
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if (func == 1) { /* output? if yes, also set the initial value */
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reg = readl(S3C_GPADAT + 4 + offset) & ~(1 << (bit >> 2));
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reg |= GET_GPIOVAL(pin_mode) << (bit >> 2);
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writel(reg, S3C_GPADAT + 4 + offset);
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}
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}
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/* 'gpio_mode' must be one of the 'GP?_*' macros */
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void s3c_gpio_mode(unsigned gpio_mode)
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{
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unsigned group, offset;
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group = GET_GROUP(gpio_mode);
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offset = group_offset[group];
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switch (group) {
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case 5: /* GPF */
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case 8: /* GPI */
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case 9: /* GPJ */
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case 13: /* GPN */
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case 14: /* GPO */
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case 15: /* GPP */
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case 16: /* GPQ */
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s3c_d2pins(offset, gpio_mode);
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break;
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case 7: /* GPH */
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case 10: /* GPK */
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case 11: /* GPL */
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s3c_d42pins(offset, gpio_mode);
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break;
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default:
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s3c_d4pins(offset, gpio_mode);
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}
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}
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