321 lines
8.6 KiB
C
321 lines
8.6 KiB
C
/*
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* Copyright (C) 2012 Alexey Galakhov
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*
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* Based on code from u-boot found somewhere on the web
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* that seems to originate from Samsung
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c-iomap.h>
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#define S5P_DMC_CONCONTROL 0x00
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#define S5P_DMC_MEMCONTROL 0x04
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#define S5P_DMC_MEMCONFIG0 0x08
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#define S5P_DMC_MEMCONFIG1 0x0C
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#define S5P_DMC_DIRECTCMD 0x10
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#define S5P_DMC_PRECHCONFIG 0x14
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#define S5P_DMC_PHYCONTROL0 0x18
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#define S5P_DMC_PHYCONTROL1 0x1C
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#define S5P_DMC_PWRDNCONFIG 0x28
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#define S5P_DMC_TIMINGAREF 0x30
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#define S5P_DMC_TIMINGROW 0x34
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#define S5P_DMC_TIMINGDATA 0x38
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#define S5P_DMC_TIMINGPOWER 0x3C
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#define S5P_DMC_PHYSTATUS 0x40
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#define S5P_DMC_MRSTATUS 0x54
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/* DRAM commands */
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#define CMD(x) ((x) << 24)
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#define BANK(x) ((x) << 16)
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#define CHIP(x) ((x) << 20)
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#define ADDR(x) (x)
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/**
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* MR definition:
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* 1 11
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* 2 1098 7654 3210
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* | | ^^^- burst length, 010=4, 011=8
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* | | ^- burst type 0=sequnential, 1=interleaved
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* | ^^^-- CAS latency
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* | ^----- test, 0=normal, 1=test
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* |^---- DLL reset, 1=yes
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* ^^^----- WR, 1=2, 2=3 etc.
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* ^------- PD, 0=fast exit, 1=low power
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*
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* EMR1 definition:
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* 1 11
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* 2 1098 7654 3210
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* | ^- DLL, 0=enable
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* | ^-- output strength, 0=full, 1=reduced
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* |^.. .^--- Rtt, 00=off, 01=75, 10=150, 11=50 Ohm
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* | ^^ ^-- Posted CAS# AL, 0-6
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* ^^ ^------ OCD: 000=OCD exit, 111=enable defaults
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* ^------ DQS#, 0=enable, 1=disable
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* ^------- RDQS enable, 0=no, 1=yes
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* ^-------- outputs, 0=enabled, 1=disabled
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*
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* EMR2 definition:
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* bit 7
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* 1 1
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* 2 1098 7654 3210
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* ^-- SRT, 0=1x (0-85 deg.C), 1=2x (>85 deg.C)
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* all other bits = 0
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*
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* EMR3 definition: all bits 0
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*/
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#define MRS CMD(0x0)
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#define PALL CMD(0x1)
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#define PRE CMD(0x2)
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#define DPD CMD(0x3)
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#define REFS CMD(0x4)
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#define REFA CMD(0x5)
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#define CKEL CMD(0x6)
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#define NOP CMD(0x7)
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#define REFSX CMD(0x8)
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#define MRR CMD(0x9)
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#define EMRS1 (MRS | BANK(1))
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#define EMRS2 (MRS | BANK(2))
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#define EMRS3 (MRS | BANK(3))
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/* Burst is (1 << S5P_DRAM_BURST), i.e. S5P_DRAM_BURST=2 for burst 4 */
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#ifndef S5P_DRAM_BURST
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/* (LP)DDR2 supports burst 4 only, make it default */
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# define S5P_DRAM_BURST 2
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#endif
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/**
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* Initialization sequences for different kinds of DRAM
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*/
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#define dcmd(x) writel((x) | CHIP(chip), base + S5P_DMC_DIRECTCMD)
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static void __bare_init s5p_dram_init_seq_lpddr(phys_addr_t base, unsigned chip)
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{
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const uint32_t emr = 0x400; /* DQS disable */
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const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
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| ((S5P_DRAM_CAS) << 4)
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| (S5P_DRAM_BURST);
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/* TODO this sequence is untested */
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dcmd(PALL); dcmd(REFA); dcmd(REFA);
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dcmd(MRS | ADDR(mr));
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dcmd(EMRS1 | ADDR(emr));
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}
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static void __bare_init s5p_dram_init_seq_lpddr2(phys_addr_t base, unsigned chip)
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{
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const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
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| ((S5P_DRAM_CAS) << 4)
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| (S5P_DRAM_BURST);
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/* TODO this sequence is untested */
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dcmd(NOP);
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dcmd(MRS | ADDR(mr));
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do {
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dcmd(MRR);
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} while (readl(base + S5P_DMC_MRSTATUS) & 0x01); /* poll DAI */
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}
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static void __bare_init s5p_dram_init_seq_ddr2(phys_addr_t base, unsigned chip)
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{
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const uint32_t emr = 0x400; /* DQS disable */
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const uint32_t mr = (((S5P_DRAM_WR) - 1) << 9)
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| ((S5P_DRAM_CAS) << 4)
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| (S5P_DRAM_BURST);
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dcmd(NOP);
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/* FIXME wait here? JEDEC recommends but nobody does */
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dcmd(PALL); dcmd(EMRS2); dcmd(EMRS3);
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dcmd(EMRS1 | ADDR(emr)); /* DQS disable */
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dcmd(MRS | ADDR(mr | 0x100)); /* DLL reset */
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dcmd(PALL); dcmd(REFA); dcmd(REFA);
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dcmd(MRS | ADDR(mr)); /* DLL no reset */
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dcmd(EMRS1 | ADDR(emr | 0x380)); /* OCD defaults */
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dcmd(EMRS1 | ADDR(emr)); /* OCD exit */
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}
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#undef dcmd
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static inline void __bare_init s5p_dram_start_dll(phys_addr_t base, uint32_t phycon1)
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{
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uint32_t pc0 = 0x00101000; /* the only legal initial value */
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uint32_t lv;
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/* Init DLL */
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writel(pc0, base + S5P_DMC_PHYCONTROL0);
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writel(phycon1, base + S5P_DMC_PHYCONTROL1);
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/* DLL on */
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pc0 |= 0x2;
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writel(pc0, base + S5P_DMC_PHYCONTROL0);
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/* DLL start */
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pc0 |= 0x1;
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writel(pc0, base + S5P_DMC_PHYCONTROL0);
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/* Find lock val */
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do {
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lv = readl(base + S5P_DMC_PHYSTATUS);
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} while ((lv & 0x7) != 0x7);
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lv >>= 6;
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lv &= 0xff; /* ctrl_lock_value[9:2] - coarse */
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pc0 |= (lv << 24); /* ctrl_force */
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writel(pc0, base + S5P_DMC_PHYCONTROL0); /* force value locking */
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}
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static inline void __bare_init s5p_dram_setup(phys_addr_t base, uint32_t mc0, uint32_t mc1,
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int bus16, uint32_t mcon)
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{
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mcon |= (S5P_DRAM_BURST) << 20;
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/* 16 or 32-bit bus ? */
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mcon |= bus16 ? 0x1000 : 0x2000;
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if (mc1)
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mcon |= 0x10000; /* two chips */
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writel(mcon, base + S5P_DMC_MEMCONTROL);
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/* Set up memory layout */
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writel(mc0, base + S5P_DMC_MEMCONFIG0);
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if (mc1)
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writel(mc1, base + S5P_DMC_MEMCONFIG1);
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/* Open page precharge policy - reasonable defaults */
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writel(0xFF000000, base + S5P_DMC_PRECHCONFIG);
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/* Set up timings */
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writel(DMC_TIMING_AREF, base + S5P_DMC_TIMINGAREF);
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writel(DMC_TIMING_ROW, base + S5P_DMC_TIMINGROW);
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writel(DMC_TIMING_DATA, base + S5P_DMC_TIMINGDATA);
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writel(DMC_TIMING_PWR, base + S5P_DMC_TIMINGPOWER);
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}
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static inline void __bare_init s5p_dram_start(phys_addr_t base)
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{
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/* Reasonable defaults and auto-refresh on */
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writel(0x0FFF1070, base + S5P_DMC_CONCONTROL);
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/* Reasonable defaults */
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writel(0xFFFF00FF, base + S5P_DMC_PWRDNCONFIG);
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}
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/*
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* Initialize LPDDR memory bank
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* TODO: this function is untested, see also init_seq function
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*/
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void __bare_init s5p_init_dram_bank_lpddr(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
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{
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/* refcount 8, 90 deg. shift */
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s5p_dram_start_dll(base, 0x00000085);
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/* LPDDR type */
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s5p_dram_setup(base, mc0, mc1, bus16, 0x100);
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/* Start-Up Commands */
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s5p_dram_init_seq_lpddr(base, 0);
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if (mc1)
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s5p_dram_init_seq_lpddr(base, 1);
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s5p_dram_start(base);
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}
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/*
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* Initialize LPDDR2 memory bank
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* TODO: this function is untested, see also init_seq function
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*/
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void __bare_init s5p_init_dram_bank_lpddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
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{
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/* refcount 8, 90 deg. shift */
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s5p_dram_start_dll(base, 0x00000085);
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/* LPDDR2 type */
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s5p_dram_setup(base, mc0, mc1, bus16, 0x200);
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/* Start-Up Commands */
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s5p_dram_init_seq_lpddr2(base, 0);
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if (mc1)
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s5p_dram_init_seq_lpddr2(base, 1);
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s5p_dram_start(base);
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}
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/*
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* Initialize DDR2 memory bank
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*/
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void __bare_init s5p_init_dram_bank_ddr2(phys_addr_t base, uint32_t mc0, uint32_t mc1, int bus16)
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{
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/* refcount 8, 180 deg. shift */
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s5p_dram_start_dll(base, 0x00000086);
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/* DDR2 type */
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s5p_dram_setup(base, mc0, mc1, bus16, 0x400);
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/* Start-Up Commands */
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s5p_dram_init_seq_ddr2(base, 0);
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if (mc1)
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s5p_dram_init_seq_ddr2(base, 1);
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s5p_dram_start(base);
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}
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#define BANK_ENABLED(base) (readl((base) + S5P_DMC_PHYCONTROL0) & 1)
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#define NUM_EXTRA_CHIPS(base) ((readl((base) + S5P_DMC_MEMCONTROL) >> 16) & 0xF)
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#define BANK_START(x) ((x) & 0xFF000000)
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#define BANK_END(x) (BANK_START(x) | ~(((x) & 0x00FF0000) << 8))
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#define BANK_LEN(x) (BANK_END(x) - BANK_START(x) + 1)
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static inline void sortswap(uint32_t *x, uint32_t *y)
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{
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if (*y < *x) {
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*x ^= *y;
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*y ^= *x;
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*x ^= *y;
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}
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}
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uint32_t s5p_get_memory_size(void)
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{
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int i;
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uint32_t len;
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uint32_t mc[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
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/* Read MEMCONFIG registers */
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if (BANK_ENABLED(S5P_DMC0_BASE)) {
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mc[0] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG0);
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if (NUM_EXTRA_CHIPS(S5P_DMC0_BASE) > 0)
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mc[1] = readl(S5P_DMC0_BASE + S5P_DMC_MEMCONFIG1);
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}
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if (BANK_ENABLED(S5P_DMC1_BASE)) {
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mc[2] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG0);
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if (NUM_EXTRA_CHIPS(S5P_DMC1_BASE) > 0)
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mc[3] = readl(S5P_DMC1_BASE + S5P_DMC_MEMCONFIG1);
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}
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/* Sort using a sorting network */
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sortswap(mc + 0, mc + 2);
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sortswap(mc + 1, mc + 3);
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sortswap(mc + 0, mc + 1);
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sortswap(mc + 2, mc + 3);
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sortswap(mc + 1, mc + 2);
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/* Is at least one chip enabled? */
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if (mc[0] == 0xFFFFFFFF)
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return 0;
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/* Determine maximum continuous region at start */
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len = BANK_LEN(mc[0]);
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for (i = 1; i < 4; ++i) {
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if (BANK_START(mc[i]) == BANK_END(mc[i - 1]) + 1)
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len += BANK_LEN(mc[i]);
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else
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break;
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}
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return len;
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}
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