52 lines
1.6 KiB
C
52 lines
1.6 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/socfpga-regs.h>
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#include <mach/reset-manager.h>
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/* Disable the watchdog (toggle reset to watchdog) */
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void watchdog_disable(void)
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{
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void __iomem *rm = (void *)CYCLONE5_RSTMGR_ADDRESS;
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uint32_t val;
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/* assert reset for watchdog */
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val = readl(rm + RESET_MGR_PER_MOD_RESET_OFS);
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val |= 1 << RSTMGR_PERMODRST_L4WD0_LSB;
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writel(val, rm + RESET_MGR_PER_MOD_RESET_OFS);
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/* deassert watchdog from reset (watchdog in not running state) */
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val = readl(rm + RESET_MGR_PER_MOD_RESET_OFS);
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val &= ~(1 << RSTMGR_PERMODRST_L4WD0_LSB);
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writel(val, rm + RESET_MGR_PER_MOD_RESET_OFS);
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}
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/* Write the reset manager register to cause reset */
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void reset_cpu(ulong addr)
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{
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/* request a warm reset */
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writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
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CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_CTRL_OFS);
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/*
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* infinite loop here as watchdog will trigger and reset
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* the processor
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*/
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while (1);
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}
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