57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
#ifndef __MACH_MMDC_H
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#define __MACH_MMDC_H
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#include <mach/imx6-regs.h>
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#define P0_IPS (void __iomem *)MX6_MMDC_P0_BASE_ADDR
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#define P1_IPS (void __iomem *)MX6_MMDC_P1_BASE_ADDR
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#define MDCTL 0x000
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#define MDPDC 0x004
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#define MDSCR 0x01c
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#define MDMISC 0x018
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#define MDREF 0x020
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#define MAPSR 0x404
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#define MPZQHWCTRL 0x800
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#define MPWLGCR 0x808
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#define MPWLDECTRL0 0x80c
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#define MPWLDECTRL1 0x810
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#define MPPDCMPR1 0x88c
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#define MPSWDAR 0x894
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#define MPRDDLCTL 0x848
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#define MPMUR 0x8b8
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#define MPDGCTRL0 0x83c
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#define MPDGCTRL1 0x840
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#define MPRDDLCTL 0x848
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#define MPWRDLCTL 0x850
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#define MPRDDLHWCTL 0x860
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#define MPWRDLHWCTL 0x864
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#define MPDGHWST0 0x87c
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#define MPDGHWST1 0x880
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#define MPDGHWST2 0x884
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#define MPDGHWST3 0x888
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#define MMDCx_MDCTL_SDE0 0x80000000
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#define MMDCx_MDCTL_SDE1 0x40000000
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#define MMDCx_MDCTL_DSIZ_16B 0x00000000
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#define MMDCx_MDCTL_DSIZ_32B 0x00010000
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#define MMDCx_MDCTL_DSIZ_64B 0x00020000
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#define MMDCx_MDMISC_DDR_4_BANKS 0x00000020
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5a8)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b0)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x524)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x51c)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x518)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x50c)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5b8)
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#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 ((void __iomem *)MX6_IOMUXC_BASE_ADDR + 0x5c0)
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int mmdc_do_write_level_calibration(void);
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int mmdc_do_dqs_calibration(void);
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#endif /* __MACH_MMDC_H */
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