334 lines
9.3 KiB
C
334 lines
9.3 KiB
C
/*
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* (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* Board support for Phytec's, i.MX35 based CPU card, called: PCM043
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*/
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#include <common.h>
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#include <command.h>
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#include <init.h>
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#include <driver.h>
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#include <environment.h>
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#include <fs.h>
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#include <gpio.h>
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#include <sizes.h>
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#include <mach/imx35-regs.h>
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#include <asm/armlinux.h>
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#include <io.h>
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#include <partition.h>
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#include <nand.h>
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#include <generated/mach-types.h>
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#include <mach/imx-nand.h>
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#include <fec.h>
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#include <fb.h>
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#include <led.h>
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#include <bootsource.h>
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#include <asm/mmu.h>
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#include <mach/weim.h>
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#include <mach/imx-ipu-fb.h>
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#include <mach/imx-pll.h>
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#include <mach/iomux-mx35.h>
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#include <mach/devices-imx35.h>
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#include <mach/generic.h>
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#include <mach/bbu.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = PHY_INTERFACE_MODE_MII,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct fb_videomode pcm043_fb_mode[] = {
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{
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/* 240x320 @ 60 Hz */
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.name = "TX090",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 38255,
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.left_margin = 144,
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.right_margin = 0,
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.upper_margin = 7,
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.lower_margin = 40,
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.hsync_len = 96,
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.vsync_len = 1,
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.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
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.vmode = FB_VMODE_NONINTERLACED,
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}, {
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/* 240x320 @ 60 Hz */
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 185925,
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.left_margin = 9,
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.right_margin = 16,
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.upper_margin = 7,
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.lower_margin = 9,
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.hsync_len = 1,
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.vsync_len = 1,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | \
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FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
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.vmode = FB_VMODE_NONINTERLACED,
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}
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};
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static struct imx_ipu_fb_platform_data ipu_fb_data = {
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.mode = pcm043_fb_mode,
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.num_modes = ARRAY_SIZE(pcm043_fb_mode),
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.framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M),
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.bpp = 16,
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};
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static int pcm043_mmu_init(void)
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{
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l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
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return 0;
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}
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postmmu_initcall(pcm043_mmu_init);
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struct gpio_led led0 = {
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.gpio = 1 * 32 + 6,
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};
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static int pcm043_devices_init(void)
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{
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uint32_t reg;
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char *envstr;
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unsigned long bbu_nand_flags = 0;
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/* CS0: Nor Flash */
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imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
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led_gpio_register(&led0);
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reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
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/* some fuses provide us vital information about connected hardware */
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if (reg & 0x20000000)
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nand_info.width = 2; /* 16 bit */
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else
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nand_info.width = 1; /* 8 bit */
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imx35_add_fec(&fec_info);
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/*
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* This platform supports NOR and NAND
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*/
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imx35_add_nand(&nand_info);
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/*
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* Up to 32MiB NOR type flash, connected to
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* CS line 0, data width is 16 bit
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*/
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
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switch (bootsource_get()) {
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case BOOTSOURCE_NAND:
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devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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envstr = "NAND";
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bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT;
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break;
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case BOOTSOURCE_NOR:
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default:
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devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
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devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */
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protect_file("/dev/env0", 1);
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envstr = "NOR";
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break;
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}
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pr_info("using environment from %s flash\n", envstr);
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imx35_add_fb(&ipu_fb_data);
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armlinux_set_architecture(MACH_TYPE_PCM043);
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imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
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bbu_nand_flags);
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return 0;
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}
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device_initcall(pcm043_devices_init);
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static iomux_v3_cfg_t pcm043_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_CTS1__UART1_CTS,
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MX35_PAD_I2C1_CLK__I2C1_SCL,
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MX35_PAD_I2C1_DAT__I2C1_SDA,
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MX35_PAD_ATA_CS0__GPIO2_6, /* LED */
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};
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static int imx35_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
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barebox_set_model("Phytec phyCORE-i.MX35");
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barebox_set_hostname("phycore-imx35");
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imx35_add_uart0();
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return 0;
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}
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console_initcall(imx35_console_init);
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static int pcm043_core_setup(void)
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{
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u32 tmp;
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, MX35_AIPS1_BASE_ADDR);
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writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4);
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writel(0x77777777, MX35_AIPS2_BASE_ADDR);
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writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40);
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writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44);
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writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48);
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writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C);
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tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50);
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writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40);
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writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44);
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writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48);
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writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C);
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tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */
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writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */
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writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */
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writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */
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writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */
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writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */
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writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */
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writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */
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writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */
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writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */
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writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */
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writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */
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writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */
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writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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writel(0x40, MX35_M3IF_BASE_ADDR);
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return 0;
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}
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core_initcall(pcm043_core_setup);
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#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
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#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
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static int do_cpufreq(int argc, char *argv[])
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{
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unsigned long freq;
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if (argc != 2)
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return COMMAND_ERROR_USAGE;
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freq = simple_strtoul(argv[1], NULL, 0);
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switch (freq) {
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case 399:
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writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
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break;
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case 532:
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writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL);
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break;
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default:
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return COMMAND_ERROR_USAGE;
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}
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printf("Switched CPU frequency to %luMHz\n", freq);
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return 0;
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}
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BAREBOX_CMD_START(cpufreq)
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.cmd = do_cpufreq,
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BAREBOX_CMD_DESC("adjust CPU frequency")
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BAREBOX_CMD_OPTS("399|532")
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BAREBOX_CMD_GROUP(CMD_GRP_HWMANIP)
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BAREBOX_CMD_END
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