134 lines
3.3 KiB
ArmAsm
134 lines
3.3 KiB
ArmAsm
/*
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* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <mach/imx1-regs.h>
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#include <asm/barebox-arm-head.h>
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#define CFG_MPCTL0_VAL 0x00321431
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#define CFG_SPCTL0_VAL 0x04002400
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#define CFG_CSCR_VAL 0x2f030403
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#define CFG_PCDR_VAL 0x000b00b8
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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.globl barebox_arm_reset_vector
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barebox_arm_reset_vector:
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bl arm_cpu_lowlevel_init
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/* Change PERCLK1DIV to 14 ie 14+1 */
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writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR)
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/* set MCU PLL Control Register 0 */
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writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0)
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/* set mpll restart bit */
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ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<21)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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/* set System PLL Control Register 0 */
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writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0)
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/* set spll restart bit */
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ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<22)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR)
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/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
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*this.....
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*
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* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
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* register 1, this stops it using the output of the PLL and thus runs at the
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* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
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* use the value set in the CM_OSC registers...regardless of what you set it
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* too! Thus, although i thought i was running at 140MHz, i'm actually running
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* at 40!..
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* Slapping this into my bootloader does the trick...
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* MRC p15,0,r0,c1,c0,0 ; read core configuration register
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* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
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* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
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* register
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*/
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MRC p15,0,r0,c1,c0,0
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ORR r0,r0,#0xC0000000
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MCR p15,0,r0,c1,c0,0
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #0x08000000
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bls 1f
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cmp pc, #0x09000000
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bhi 1f
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b imx1_barebox_entry
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1:
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/* SDRAM Setup */
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/* Precharge cmd, CAS = 2 */
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writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
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/* Issue Precharge all Command */
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writel(0x0, 0x08200000)
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/* Autorefresh cmd, CAS = 2 */
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writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
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ldr r0, =0x08000000
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ldr r1, =0x0 /* Issue AutoRefresh Command */
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
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/* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */
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writel(0x0, 0x08223000)
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/* Set to Normal Mode CAS 2 */
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writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
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b imx1_barebox_entry
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